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mem_byte_sel: out std_logic_vector(3 downto 0);
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mem_byte_sel: out std_logic_vector(3 downto 0);
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mem_write : out std_logic;
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mem_write : out std_logic;
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mem_pause : in std_logic);
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mem_pause : in std_logic);
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end component;
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end component;
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-- For test bench (not synthesizable)
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component ram
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component ram
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generic(load_file_name : string);
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generic(memory_type : string := "GENERIC");
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port(clk : in std_logic;
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port(clk : in std_logic;
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mem_byte_sel : in std_logic_vector(3 downto 0);
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mem_byte_sel : in std_logic_vector(3 downto 0);
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mem_write : in std_logic;
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mem_write : in std_logic;
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mem_address : in std_logic_vector;
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mem_address : in std_logic_vector(31 downto 0);
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mem_data_w : in std_logic_vector(31 downto 0);
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mem_data : inout std_logic_vector(31 downto 0));
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mem_data_r : out std_logic_vector(31 downto 0));
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end component; --ram
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end component; --ram
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component uart
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component uart
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generic(save_file_name : string := "UNUSED");
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generic(log_file : string := "UNUSED");
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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uart_sel : in std_logic;
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uart_sel : in std_logic;
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data : in std_logic_vector(7 downto 0);
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data : in std_logic_vector(7 downto 0);
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read_pin : in std_logic;
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uart_read : in std_logic;
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write_pin : out std_logic;
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uart_write : out std_logic;
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pause : out std_logic);
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pause : out std_logic);
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end component; --uart
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end component; --uart
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component plasma
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generic(memory_type : string := "GENERIC";
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log_file : string := "UNUSED");
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port(clk_in : in std_logic;
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reset_in : in std_logic;
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intr_in : in std_logic;
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uart_read : in std_logic;
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uart_write : out std_logic;
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mem_address_out : out std_logic_vector(31 downto 0);
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mem_data : inout std_logic_vector(31 downto 0);
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mem_byte_sel_out : out std_logic_vector(3 downto 0);
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mem_write_out : out std_logic;
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mem_pause_in : in std_logic);
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end component; --plasma
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end; --package mlite_pack
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end; --package mlite_pack
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package body mlite_pack is
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package body mlite_pack is
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function add_1(a:integer) return integer is
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function add_1(a:integer) return integer is
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