| Line 111... |
Line 111... |
constant branch_gtz : branch_function_type := "101";
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constant branch_gtz : branch_function_type := "101";
|
constant branch_yes : branch_function_type := "110";
|
constant branch_yes : branch_function_type := "110";
|
|
|
-- mode(32=1,16=2,8=3), signed, write
|
-- mode(32=1,16=2,8=3), signed, write
|
subtype mem_source_type is std_logic_vector(3 downto 0);
|
subtype mem_source_type is std_logic_vector(3 downto 0);
|
constant mem_none : mem_source_type := "0000";
|
constant mem_fetch : mem_source_type := "0000";
|
constant mem_read32 : mem_source_type := "0100";
|
constant mem_read32 : mem_source_type := "0100";
|
constant mem_write32 : mem_source_type := "0101";
|
constant mem_write32 : mem_source_type := "0101";
|
constant mem_read16 : mem_source_type := "1000";
|
constant mem_read16 : mem_source_type := "1000";
|
constant mem_read16s : mem_source_type := "1010";
|
constant mem_read16s : mem_source_type := "1010";
|
constant mem_write16 : mem_source_type := "1001";
|
constant mem_write16 : mem_source_type := "1001";
|
| Line 172... |
Line 172... |
rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
|
rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
|
wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0));
|
wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0));
|
END COMPONENT;
|
END COMPONENT;
|
|
|
-- For Altera
|
-- For Altera
|
component lpm_ram_io
|
component LPM_RAM_DQ
|
GENERIC (
|
generic (
|
intended_device_family : string;
|
LPM_WIDTH : natural; -- MUST be greater than 0
|
lpm_width : natural;
|
LPM_WIDTHAD : natural; -- MUST be greater than 0
|
lpm_widthad : natural;
|
LPM_NUMWORDS : natural := 0;
|
lpm_indata : string := "REGISTERED";
|
LPM_INDATA : string := "REGISTERED";
|
lpm_address_control : string := "UNREGISTERED";
|
LPM_ADDRESS_CONTROL: string := "REGISTERED";
|
lpm_outdata : string := "UNREGISTERED";
|
LPM_OUTDATA : string := "REGISTERED";
|
lpm_file : string := "code.hex";
|
LPM_FILE : string := "UNUSED";
|
use_eab : string := "ON";
|
LPM_TYPE : string := "LPM_RAM_DQ";
|
lpm_type : string := "LPM_RAM_DQ");
|
USE_EAB : string := "OFF";
|
PORT (
|
INTENDED_DEVICE_FAMILY : string := "UNUSED";
|
outenab : in std_logic;
|
LPM_HINT : string := "UNUSED");
|
address : in std_logic_vector(lpm_widthad-1 downto 0);
|
port (
|
inclock : in std_logic;
|
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
|
we : in std_logic;
|
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
|
dio : inout std_logic_vector(lpm_width-1 downto 0));
|
INCLOCK : in std_logic := '0';
|
end component; --lpm_ram_io
|
OUTCLOCK : in std_logic := '0';
|
|
WE : in std_logic;
|
|
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
|
|
end component;
|
|
|
-- For Xilinx
|
-- For Xilinx
|
component ramb4_s16_s16
|
component ramb4_s16_s16
|
port (
|
port (
|
clka : in std_logic;
|
clka : in std_logic;
|
| Line 341... |
Line 344... |
generic(memory_type : string := "GENERIC");
|
generic(memory_type : string := "GENERIC");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
mem_byte_sel : in std_logic_vector(3 downto 0);
|
mem_byte_sel : in std_logic_vector(3 downto 0);
|
mem_write : in std_logic;
|
mem_write : in std_logic;
|
mem_address : in std_logic_vector(31 downto 0);
|
mem_address : in std_logic_vector(31 downto 0);
|
mem_data : inout std_logic_vector(31 downto 0));
|
mem_data_w : in std_logic_vector(31 downto 0);
|
|
mem_data_r : out std_logic_vector(31 downto 0));
|
end component; --ram
|
end component; --ram
|
|
|
component uart
|
component uart
|
generic(log_file : string := "UNUSED");
|
generic(log_file : string := "UNUSED");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
| Line 366... |
Line 370... |
|
|
uart_read : in std_logic;
|
uart_read : in std_logic;
|
uart_write : out std_logic;
|
uart_write : out std_logic;
|
|
|
mem_address_out : out std_logic_vector(31 downto 0);
|
mem_address_out : out std_logic_vector(31 downto 0);
|
mem_data : inout std_logic_vector(31 downto 0);
|
mem_data : out std_logic_vector(31 downto 0);
|
mem_byte_sel_out : out std_logic_vector(3 downto 0);
|
mem_byte_sel_out : out std_logic_vector(3 downto 0);
|
mem_write_out : out std_logic;
|
mem_write_out : out std_logic;
|
mem_pause_in : in std_logic);
|
mem_pause_in : in std_logic);
|
end component; --plasma
|
end component; --plasma
|
|
|
|
component plasma_if
|
|
generic(memory_type : string := "ALTERA";
|
|
log_file : string := "UNUSED");
|
|
port(clk_in : in std_logic;
|
|
reset_n : in std_logic;
|
|
uart_read : in std_logic;
|
|
uart_write : out std_logic;
|
|
|
|
address : out std_logic_vector(31 downto 0);
|
|
data : out std_logic_vector(31 downto 0);
|
|
we_n : out std_logic;
|
|
oe_n : out std_logic;
|
|
be_n : out std_logic_vector(3 downto 0);
|
|
sram0_cs_n : out std_logic;
|
|
sram1_cs_n : out std_logic);
|
|
end component; --plasma_if
|
|
|
end; --package mlite_pack
|
end; --package mlite_pack
|
|
|
package body mlite_pack is
|
package body mlite_pack is
|
|
|
function add_1(a:integer) return integer is
|
function add_1(a:integer) return integer is
|
