| Line 20... |
Line 20... |
--make HIGH_Z equal to ZERO if compiler complains
|
--make HIGH_Z equal to ZERO if compiler complains
|
constant HIGH_Z : std_logic_vector(31 downto 0) :=
|
constant HIGH_Z : std_logic_vector(31 downto 0) :=
|
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
|
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
|
|
|
-- type alu_function_type is (alu_nothing, alu_add, alu_subtract,
|
-- type alu_function_type is (alu_nothing, alu_add, alu_subtract,
|
-- alu_less_than, alu_less_than_signed, alu_equal, alu_not_equal,
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-- alu_less_than, alu_less_than_signed,
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-- alu_ltz, alu_lez, alu_eqz, alu_nez, alu_gez, alu_gtz,
|
|
-- alu_or, alu_and, alu_xor, alu_nor);
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-- alu_or, alu_and, alu_xor, alu_nor);
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subtype alu_function_type is std_logic_vector(4 downto 0);
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subtype alu_function_type is std_logic_vector(3 downto 0);
|
constant alu_nothing : alu_function_type := "00000";
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constant alu_nothing : alu_function_type := "0000";
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constant alu_add : alu_function_type := "00010";
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constant alu_add : alu_function_type := "0001";
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constant alu_subtract : alu_function_type := "00011";
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constant alu_subtract : alu_function_type := "0010";
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constant alu_less_than : alu_function_type := "00100";
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constant alu_less_than : alu_function_type := "0011";
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constant alu_less_than_signed : alu_function_type := "00101";
|
constant alu_less_than_signed : alu_function_type := "0100";
|
constant alu_equal : alu_function_type := "00110";
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constant alu_or : alu_function_type := "0101";
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constant alu_not_equal : alu_function_type := "00111";
|
constant alu_and : alu_function_type := "0110";
|
constant alu_ltz : alu_function_type := "01000";
|
constant alu_xor : alu_function_type := "0111";
|
constant alu_lez : alu_function_type := "01001";
|
constant alu_nor : alu_function_type := "1000";
|
constant alu_eqz : alu_function_type := "01010";
|
|
constant alu_nez : alu_function_type := "01011";
|
|
constant alu_gez : alu_function_type := "01100";
|
|
constant alu_gtz : alu_function_type := "01101";
|
|
constant alu_or : alu_function_type := "01110";
|
|
constant alu_and : alu_function_type := "01111";
|
|
constant alu_xor : alu_function_type := "10001";
|
|
constant alu_nor : alu_function_type := "10010";
|
|
|
|
-- type shift_function_type is (
|
-- type shift_function_type is (
|
-- shift_nothing, shift_left_unsigned,
|
-- shift_nothing, shift_left_unsigned,
|
-- shift_right_signed, do_right_unsigned);
|
-- shift_right_signed, do_right_unsigned);
|
subtype shift_function_type is std_logic_vector(1 downto 0);
|
subtype shift_function_type is std_logic_vector(1 downto 0);
|
| Line 139... |
Line 130... |
|
|
-- For Altera
|
-- For Altera
|
COMPONENT lpm_add_sub
|
COMPONENT lpm_add_sub
|
GENERIC (
|
GENERIC (
|
lpm_width : NATURAL;
|
lpm_width : NATURAL;
|
lpm_direction : STRING;
|
lpm_direction : STRING := "UNUSED";
|
lpm_type : STRING;
|
lpm_type : STRING;
|
lpm_hint : STRING);
|
lpm_hint : STRING);
|
PORT (
|
PORT (
|
dataa : IN STD_LOGIC_VECTOR (32 DOWNTO 0);
|
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
|
add_sub : IN STD_LOGIC ;
|
add_sub : IN STD_LOGIC ;
|
datab : IN STD_LOGIC_VECTOR (32 DOWNTO 0);
|
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
|
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 0));
|
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0));
|
END COMPONENT;
|
END COMPONENT;
|
|
|
-- For Altera
|
-- For Altera
|
COMPONENT lpm_ram_dp
|
COMPONENT lpm_ram_dp
|
GENERIC (
|
GENERIC (
|
| Line 165... |
Line 156... |
use_eab : STRING;
|
use_eab : STRING;
|
lpm_type : STRING);
|
lpm_type : STRING);
|
PORT (
|
PORT (
|
wren : IN STD_LOGIC ;
|
wren : IN STD_LOGIC ;
|
wrclock : IN STD_LOGIC ;
|
wrclock : IN STD_LOGIC ;
|
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
|
q : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
|
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
data : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
|
rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
|
rdaddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0);
|
wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0));
|
wraddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0));
|
END COMPONENT;
|
END COMPONENT;
|
|
|
-- For Altera
|
-- For Altera
|
component LPM_RAM_DQ
|
component LPM_RAM_DQ
|
generic (
|
generic (
|
| Line 430... |
Line 421... |
|
|
end; --package mlite_pack
|
end; --package mlite_pack
|
|
|
package body mlite_pack is
|
package body mlite_pack is
|
|
|
function add_1(a:integer) return integer is
|
|
begin
|
|
return a+1;
|
|
end; --function
|
|
|
|
function bv_to_integer(bv: in std_logic_vector) return integer is
|
function bv_to_integer(bv: in std_logic_vector) return integer is
|
variable result : integer;
|
variable result : integer;
|
variable b : integer;
|
variable b : integer;
|
begin
|
begin
|
result := 0;
|
result := 0;
|
| Line 452... |
Line 438... |
result := result * 2 + b;
|
result := result * 2 + b;
|
end loop;
|
end loop;
|
return result;
|
return result;
|
end; --function bv_to_integer
|
end; --function bv_to_integer
|
|
|
|
|
function bv_adder(a : in std_logic_vector(32 downto 0);
|
function bv_adder(a : in std_logic_vector(32 downto 0);
|
b : in std_logic_vector(32 downto 0);
|
b : in std_logic_vector(32 downto 0);
|
do_add: in std_logic) return std_logic_vector is
|
do_add: in std_logic) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable bb : std_logic_vector(32 downto 0);
|
variable bb : std_logic_vector(32 downto 0);
|
| Line 475... |
Line 462... |
(a(index) and bb(index));
|
(a(index) and bb(index));
|
end loop;
|
end loop;
|
return result;
|
return result;
|
end; --function
|
end; --function
|
|
|
|
|
function bv_adder_lookahead(
|
function bv_adder_lookahead(
|
a : in std_logic_vector(32 downto 0);
|
a : in std_logic_vector(32 downto 0);
|
b : in std_logic_vector(32 downto 0);
|
b : in std_logic_vector(32 downto 0);
|
do_add: in std_logic) return std_logic_vector is
|
do_add: in std_logic) return std_logic_vector is
|
variable carry : std_logic_vector(32 downto 0);
|
variable carry : std_logic_vector(32 downto 0);
|
| Line 521... |
Line 509... |
end loop;
|
end loop;
|
result := (a xor bb) xor carry;
|
result := (a xor bb) xor carry;
|
return result;
|
return result;
|
end; --function
|
end; --function
|
|
|
|
|
function bv_negate(a : in std_logic_vector) return std_logic_vector is
|
function bv_negate(a : in std_logic_vector) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable not_a : std_logic_vector(31 downto 0);
|
variable not_a : std_logic_vector(31 downto 0);
|
variable result : std_logic_vector(31 downto 0);
|
variable result : std_logic_vector(31 downto 0);
|
begin
|
begin
|
| Line 536... |
Line 525... |
carry_in := carry_in and not_a(index);
|
carry_in := carry_in and not_a(index);
|
end loop;
|
end loop;
|
return result;
|
return result;
|
end; --function
|
end; --function
|
|
|
|
|
function bv_increment(a : in std_logic_vector(31 downto 2)
|
function bv_increment(a : in std_logic_vector(31 downto 2)
|
) return std_logic_vector is
|
) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable result : std_logic_vector(31 downto 2);
|
variable result : std_logic_vector(31 downto 2);
|
begin
|
begin
|
| Line 550... |
Line 540... |
carry_in := a(index) and carry_in;
|
carry_in := a(index) and carry_in;
|
end loop;
|
end loop;
|
return result;
|
return result;
|
end; --function
|
end; --function
|
|
|
|
|
function bv_inc6(a : in std_logic_vector
|
function bv_inc6(a : in std_logic_vector
|
) return std_logic_vector is
|
) return std_logic_vector is
|
variable carry_in : std_logic;
|
variable carry_in : std_logic;
|
variable result : std_logic_vector(5 downto 0);
|
variable result : std_logic_vector(5 downto 0);
|
begin
|
begin
|
