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[/] [mlite/] [trunk/] [vhdl/] [mult.vhd] - Diff between revs 99 and 117
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| Rev 99 |
Rev 117 |
| Line 35... |
Line 35... |
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity mult is
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entity mult is
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generic(adder_type : string := "GENERIC");
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generic(adder_type : string := "GENERIC";
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mult_type : string := "GENERIC");
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port(clk : in std_logic;
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port(clk : in std_logic;
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a, b : in std_logic_vector(31 downto 0);
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a, b : in std_logic_vector(31 downto 0);
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mult_func : in mult_function_type;
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mult_func : in mult_function_type;
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c_mult : out std_logic_vector(31 downto 0);
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c_mult : out std_logic_vector(31 downto 0);
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pause_out : out std_logic);
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pause_out : out std_logic);
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Line 237... |
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end process;
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end process;
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generic_adder:
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generic_adder:
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if adder_type /= "ALTERA" generate
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if adder_type = "GENERIC" generate
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sum <= (aa + bb) when do_mult_reg = '1' else
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sum <= (aa + bb) when do_mult_reg = '1' else
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(aa - bb);
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(aa - bb);
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end generate; --generic_adder
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end generate; --generic_adder
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--For Altera
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--For Altera
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