Line 1... |
Line 1... |
---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Multiplication and Division Unit
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-- TITLE: Multiplication and Division Unit
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHORS: Steve Rhoads (rhoadss@yahoo.com)
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-- Matthias Gruenewald
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-- DATE CREATED: 1/31/01
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-- DATE CREATED: 1/31/01
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-- FILENAME: mult.vhd
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-- FILENAME: mult.vhd
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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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Line 29... |
Line 30... |
-- answer_reg += 1;
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-- answer_reg += 1;
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-- reg_a -= reg_b;
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-- reg_a -= reg_b;
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-- }
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-- }
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-- reg_b = reg_b >> 1;
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-- reg_b = reg_b >> 1;
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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--library ieee, MLITE_LIB;
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--use MLITE_LIB.all;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity mult is
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entity mult is
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generic(adder_type : string := "GENERIC";
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generic(adder_type : string := "GENERIC";
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mult_type : string := "GENERIC");
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mult_type : string := "GENERIC");
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Line 45... |
Line 49... |
c_mult : out std_logic_vector(31 downto 0);
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c_mult : out std_logic_vector(31 downto 0);
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pause_out : out std_logic);
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pause_out : out std_logic);
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end; --entity mult
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end; --entity mult
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architecture logic of mult is
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architecture logic of mult is
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-- type mult_function_type is (
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-- type mult_function_type is (
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-- mult_nothing, mult_read_lo, mult_read_hi, mult_write_lo,
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-- mult_nothing, mult_read_lo, mult_read_hi, mult_write_lo,
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-- mult_write_hi, mult_mult, mult_divide, mult_signed_divide);
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-- mult_write_hi, mult_mult, mult_divide, mult_signed_divide);
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signal do_mult_reg : std_logic;
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signal do_mult_reg : std_logic;
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signal do_signed_reg : std_logic;
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signal do_signed_reg : std_logic;
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Line 56... |
Line 61... |
signal reg_a : std_logic_vector(31 downto 0);
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signal reg_a : std_logic_vector(31 downto 0);
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signal reg_b : std_logic_vector(63 downto 0);
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signal reg_b : std_logic_vector(63 downto 0);
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signal answer_reg : std_logic_vector(31 downto 0);
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signal answer_reg : std_logic_vector(31 downto 0);
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signal aa, bb : std_logic_vector(33 downto 0);
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signal aa, bb : std_logic_vector(33 downto 0);
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signal sum : std_logic_vector(33 downto 0);
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signal sum : std_logic_vector(33 downto 0);
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signal sum2 : std_logic_vector(67 downto 0);
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signal reg_a_times3 : std_logic_vector(33 downto 0);
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signal reg_a_times3 : std_logic_vector(33 downto 0);
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signal sign_extend_sig : std_logic;
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--Used in Xilinx tri-state area optimizated version
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signal SUB_Y, A_PROCESSED, B_PROCESSED, A_REG, B_REG : std_logic_vector(31 downto 0);
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signal DIV_Y, DIV_Y_IN, DIV_Y_IN_CALC, DIV_Y_IN_INIT, Y_IN, Y_IN2, MULT_Y, Y : std_logic_vector(63 downto 0) := (others => '0');
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signal SAVE_Y, SAVE_DIV_Y, MULT_ND, MULT_RDY, DO_SIGNED, DIV_ND : std_logic;
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signal DIV_COUNT, INVERT_A, INVERT_B, INVERT_Y, DIV_RDY : std_logic;
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signal DIV_COUNTER : std_logic_vector(4 downto 0);
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signal PAUSE_IN, SAVE_PAUSE, PAUSE : std_logic := '0';
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signal MULT_RFD : std_logic;
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signal a_temp_sig, a_neg_sig, b_neg_sig : std_logic_vector(31 downto 0);
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signal b_temp_sig : std_logic_vector(63 downto 0);
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signal a_msb, b_msb : std_logic;
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signal answer_temp_sig : std_logic_vector(31 downto 0);
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signal aa_select : std_logic_vector(3 downto 0);
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signal bb_select : std_logic_vector(1 downto 0);
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signal a_select : std_logic_vector(4 downto 0);
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signal b_select : std_logic_vector(11 downto 0);
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signal answer_select : std_logic_vector(2 downto 0);
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begin
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begin
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--sum = aa + bb
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generic_adder: if adder_type = "GENERIC" generate
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sum <= (aa + bb) when do_mult_reg = '1' else
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(aa - bb);
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end generate; --generic_adder
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--For Altera: sum = aa + bb
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lpm_adder: if adder_type = "ALTERA" generate
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lpm_add_sub_component : lpm_add_sub
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GENERIC MAP (
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lpm_width => 34,
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lpm_direction => "UNUSED",
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lpm_type => "LPM_ADD_SUB",
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lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
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)
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PORT MAP (
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dataa => aa,
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add_sub => do_mult_reg,
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datab => bb,
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result => sum
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);
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end generate; --lpm_adder
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-- Negate signals
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a_neg_sig <= bv_negate(a);
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b_neg_sig <= bv_negate(b);
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sign_extend_sig <= do_signed_reg and do_mult_reg;
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-- Result
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c_mult <= reg_b(31 downto 0) when mult_func=mult_read_lo else
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reg_b(63 downto 32) when mult_func=mult_read_hi else
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ZERO;
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GENERIC_MULT: if MULT_TYPE="GENERIC" generate
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|
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--multiplication/division unit
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--multiplication/division unit
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mult_proc: process(clk, a, b, mult_func,
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mult_proc: process(clk, a, b, mult_func,
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do_mult_reg, do_signed_reg, count_reg,
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do_mult_reg, do_signed_reg, count_reg,
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reg_a, reg_b, answer_reg, sum, reg_a_times3)
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reg_a, reg_b, answer_reg, sum, reg_a_times3)
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variable do_mult_temp : std_logic;
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variable do_mult_temp : std_logic;
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Line 73... |
Line 135... |
variable answer_temp : std_logic_vector(31 downto 0);
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variable answer_temp : std_logic_vector(31 downto 0);
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variable start : std_logic;
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variable start : std_logic;
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variable do_write : std_logic;
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variable do_write : std_logic;
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variable do_hi : std_logic;
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variable do_hi : std_logic;
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variable sign_extend : std_logic;
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variable sign_extend : std_logic;
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variable a_neg : std_logic_vector(31 downto 0);
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variable b_neg : std_logic_vector(31 downto 0);
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begin
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begin
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do_mult_temp := do_mult_reg;
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do_mult_temp := do_mult_reg;
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do_signed_temp := do_signed_reg;
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do_signed_temp := do_signed_reg;
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count_temp := count_reg;
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count_temp := count_reg;
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Line 119... |
Line 179... |
end case;
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end case;
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if start = '1' then
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if start = '1' then
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count_temp := "000000";
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count_temp := "000000";
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answer_temp := ZERO;
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answer_temp := ZERO;
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a_neg := bv_negate(a);
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b_neg := bv_negate(b);
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if do_mult_temp = '0' then
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if do_mult_temp = '0' then
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b_temp(63) := '0';
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b_temp(63) := '0';
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if mult_func /= mult_signed_divide or a(31) = '0' then
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if mult_func /= mult_signed_divide or a(31) = '0' then
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a_temp := a;
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a_temp := a;
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else
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else
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a_temp := a_neg;
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a_temp := a_neg_sig;
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end if;
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end if;
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if mult_func /= mult_signed_divide or b(31) = '0' then
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if mult_func /= mult_signed_divide or b(31) = '0' then
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b_temp(62 downto 31) := b;
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b_temp(62 downto 31) := b;
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else
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else
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b_temp(62 downto 31) := b_neg;
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b_temp(62 downto 31) := b_neg_sig;
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end if;
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end if;
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b_temp(30 downto 0) := ZERO(30 downto 0);
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b_temp(30 downto 0) := ZERO(30 downto 0);
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else --multiply
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else --multiply
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if do_signed_temp = '0' or b(31) = '0' then
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if do_signed_temp = '0' or b(31) = '0' then
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a_temp := a;
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a_temp := a;
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b_temp(31 downto 0) := b;
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b_temp(31 downto 0) := b;
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else
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else
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a_temp := a_neg;
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a_temp := a_neg_sig;
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b_temp(31 downto 0) := b_neg;
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b_temp(31 downto 0) := b_neg_sig;
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end if;
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end if;
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b_temp(63 downto 32) := ZERO;
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b_temp(63 downto 32) := ZERO;
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end if;
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end if;
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elsif do_write = '1' then
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elsif do_write = '1' then
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if do_hi = '0' then
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if do_hi = '0' then
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Line 224... |
Line 282... |
if count_reg(5) = '0' and mult_func/= mult_nothing and start = '0' then
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if count_reg(5) = '0' and mult_func/= mult_nothing and start = '0' then
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pause_out <= '1';
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pause_out <= '1';
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else
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else
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pause_out <= '0';
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pause_out <= '0';
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end if;
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end if;
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end process;
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end generate;
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AREA_OPTIMIZED_MULT: if MULT_TYPE="AREA_OPTIMIZED" generate
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--Xilinx Tristate size optimization by Matthias Gruenewald
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--multiplication/division unit
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mult_proc: process(a, b, clk, count_reg, do_mult_reg, do_signed_reg, mult_func, reg_b, sum)
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variable do_mult_temp : std_logic;
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variable do_signed_temp : std_logic;
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variable count_temp : std_logic_vector(5 downto 0);
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variable start : std_logic;
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variable do_write : std_logic;
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variable do_hi : std_logic;
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variable sign_extend : std_logic;
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begin
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do_mult_temp := do_mult_reg;
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do_signed_temp := do_signed_reg;
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count_temp := count_reg;
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sign_extend := do_signed_reg and do_mult_reg;
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sign_extend_sig <= sign_extend;
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start := '0';
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do_write := '0';
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do_hi := '0';
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a_select <= (others => '0');
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b_select <= (others => '0');
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aa_select <= (others => '0');
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bb_select <= (others => '0');
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answer_select <= (others => '0');
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case mult_func is
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case mult_func is
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when mult_read_lo =>
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when mult_read_lo =>
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c_mult <= reg_b(31 downto 0);
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when mult_read_hi =>
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when mult_read_hi =>
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c_mult <= reg_b(63 downto 32);
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do_hi := '1';
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when mult_write_lo =>
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do_write := '1';
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when mult_write_hi =>
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do_write := '1';
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do_hi := '1';
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when mult_mult =>
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start := '1';
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do_mult_temp := '1';
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do_signed_temp := '0';
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when mult_signed_mult =>
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start := '1';
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do_mult_temp := '1';
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do_signed_temp := '1';
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when mult_divide =>
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start := '1';
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do_mult_temp := '0';
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do_signed_temp := '0';
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when mult_signed_divide =>
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start := '1';
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do_mult_temp := '0';
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do_signed_temp := a(31) xor b(31);
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when others =>
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when others =>
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c_mult <= ZERO;
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end case;
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end case;
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if start = '1' then
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count_temp := "000000";
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answer_select(0)<='1';
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--answer_temp := ZERO;
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if do_mult_temp = '0' then
|
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--b_temp(63) := '0';
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if mult_func /= mult_signed_divide or a(31) = '0' then
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a_select(0) <= '1';
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--a_temp := a;
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else
|
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a_select(1) <= '1';
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--a_temp := a_neg;
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end if;
|
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if mult_func /= mult_signed_divide or b(31) = '0' then
|
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b_select(0) <= '1';
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--b_temp(62 downto 31) := b;
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else
|
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b_select(1) <= '1';
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--b_temp(62 downto 31) := b_neg;
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end if;
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--b_temp(30 downto 0) := ZERO(30 downto 0);
|
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else --multiply
|
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if do_signed_temp = '0' or b(31) = '0' then
|
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a_select(2) <= '1';
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--a_temp := a;
|
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b_select(2) <= '1';
|
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--b_temp(31 downto 0) := b;
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else
|
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a_select(3) <= '1';
|
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--a_temp := a_neg;
|
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b_select(3) <= '1';
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--b_temp(31 downto 0) := b_neg;
|
|
end if;
|
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--b_temp(63 downto 32) := ZERO;
|
|
end if;
|
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elsif do_write = '1' then
|
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if do_hi = '0' then
|
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b_select(4) <= '1';
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--b_temp(31 downto 0) := a;
|
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else
|
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b_select(5) <= '1';
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--b_temp(63 downto 32) := a;
|
|
end if;
|
|
end if;
|
|
|
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if do_mult_reg = '0' then --division
|
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aa_select(0) <= '1';
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--aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;
|
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bb_select(0) <= '1';
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--bb <= reg_b(33 downto 0);
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else --multiplication two-bits at a time
|
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case reg_b(1 downto 0) is
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when "00" =>
|
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aa_select(1) <= '1';
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--aa <= "00" & ZERO;
|
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when "01" =>
|
|
aa_select(2) <= '1';
|
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--aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;
|
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when "10" =>
|
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aa_select(3) <= '1';
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--aa <= (reg_a(31) and sign_extend) & reg_a & '0';
|
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when others =>
|
|
--aa_select(4) <= '1';
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--aa <= reg_a_times3;
|
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end case;
|
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bb_select(1) <= '1';
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--bb <= (reg_b(63) and sign_extend) & (reg_b(63) and sign_extend) & reg_b(63 downto 32);
|
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end if;
|
|
|
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if count_reg(5) = '0' and start = '0' then
|
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count_temp := bv_inc6(count_reg);
|
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if do_mult_reg = '0' then --division
|
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--answer_temp(31 downto 1) := answer_reg(30 downto 0);
|
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if reg_b(63 downto 32) = ZERO and sum(32) = '0' then
|
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a_select(4) <= '1';
|
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--a_temp := sum(31 downto 0); --aa=aa-bb;
|
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answer_select(1) <= '1';
|
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--answer_temp(0) := '1';
|
|
else
|
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answer_select(2) <= '1';
|
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--answer_temp(0) := '0';
|
|
end if;
|
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if count_reg /= "011111" then
|
|
--b_temp(62 downto 0) := reg_b(63 downto 1);
|
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b_select(6) <= '1';
|
|
else --done with divide
|
|
--b_temp(63 downto 32) := a_temp;
|
|
if do_signed_reg = '0' then
|
|
b_select(7) <= '1';
|
|
--b_temp(31 downto 0) := answer_temp;
|
|
else
|
|
b_select(8) <= '1';
|
|
--b_temp(31 downto 0) := bv_negate(answer_temp);
|
|
end if;
|
|
end if;
|
|
else -- mult_mode
|
|
b_select(9) <= '1';
|
|
--b_temp(63 downto 30) := sum;
|
|
--b_temp(29 downto 0) := reg_b(31 downto 2);
|
|
if count_reg = "001000" and sign_extend = '0' and --early stop
|
|
reg_b(15 downto 0) = ZERO(15 downto 0) then
|
|
count_temp := "111111";
|
|
b_select(10) <= '1';
|
|
--b_temp(31 downto 0) := reg_b(47 downto 16);
|
|
end if;
|
|
if count_reg = "000100" and sign_extend = '0' and --early stop
|
|
reg_b(23 downto 0) = ZERO(23 downto 0) then
|
|
count_temp := "111111";
|
|
b_select(11) <= '1';
|
|
--b_temp(31 downto 0) := reg_b(55 downto 24);
|
|
end if;
|
|
count_temp(5) := count_temp(4);
|
|
end if;
|
|
end if;
|
|
|
|
if rising_edge(clk) then
|
|
do_mult_reg <= do_mult_temp;
|
|
do_signed_reg <= do_signed_temp;
|
|
count_reg <= count_temp;
|
|
reg_a <= a_temp_sig;
|
|
reg_b <= b_temp_sig;
|
|
answer_reg <= answer_temp_sig;
|
|
if start = '1' then
|
|
reg_a_times3 <= ((a_temp_sig(31) and do_signed_temp) & a_temp_sig & '0') +
|
|
((a_temp_sig(31) and do_signed_temp) & (a_temp_sig(31) and do_signed_temp) & a_temp_sig);
|
|
end if;
|
|
end if;
|
|
|
|
if count_reg(5) = '0' and mult_func/= mult_nothing and start = '0' then
|
|
pause_out <= '1';
|
|
else
|
|
pause_out <= '0';
|
|
end if;
|
|
|
end process;
|
end process;
|
|
|
|
|
generic_adder:
|
-- Arguments
|
if adder_type = "GENERIC" generate
|
a_msb <= reg_a(31) and sign_extend_sig;
|
sum <= (aa + bb) when do_mult_reg = '1' else
|
aa <= a_msb & a_msb & reg_a when aa_select(0)='1' else
|
(aa - bb);
|
"00" & ZERO when aa_select(1)='1' else
|
end generate; --generic_adder
|
a_msb & a_msb & reg_a when aa_select(2)='1' else
|
|
a_msb & reg_a & '0' when aa_select(3)='1' else
|
|
reg_a_times3;
|
|
|
|
b_msb <= reg_b(63) and sign_extend_sig;
|
|
bb <= reg_b(33 downto 0) when bb_select(0)='1' else (others => 'Z');
|
|
bb <= b_msb & b_msb & reg_b(63 downto 32) when bb_select(1)='1' else (others => 'Z');
|
|
|
|
-- Divide: Init
|
|
a_temp_sig <= a when a_select(0)='1' else (others => 'Z');
|
|
a_temp_sig <= a_neg_sig when a_select(1)='1' else (others => 'Z');
|
|
b_temp_sig <= '0' & b & ZERO(30 downto 0) when b_select(0)='1' else (others => 'Z');
|
|
b_temp_sig <= '0' & b_neg_sig & ZERO(30 downto 0) when b_select(1)='1' else (others => 'Z');
|
|
|
|
-- Multiply: Init
|
|
a_temp_sig <= a when a_select(2)='1' else (others => 'Z');
|
|
b_temp_sig <= ZERO & b when b_select(2)='1' else (others => 'Z');
|
|
a_temp_sig <= a_neg_sig when a_select(3)='1' else (others => 'Z');
|
|
b_temp_sig <= ZERO & b_neg_sig when b_select(3)='1' else (others => 'Z');
|
|
|
|
-- Intermediate results
|
|
b_temp_sig <= reg_b(63 downto 32) & a when b_select(4)='1' else (others => 'Z');
|
|
b_temp_sig <= a & reg_b(31 downto 0) when b_select(5)='1' else (others => 'Z');
|
|
|
|
-- Divide: Operation
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|
a_temp_sig <= sum(31 downto 0) when a_select(4)='1' else (others => 'Z');
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|
b_temp_sig <= reg_b(63) & reg_b(63 downto 1) when b_select(6)='1' else (others => 'Z');
|
|
b_temp_sig <= a_temp_sig & answer_temp_sig when b_select(7)='1' else (others => 'Z');
|
|
b_temp_sig <= a_temp_sig & bv_negate(answer_temp_sig) when b_select(8)='1' else (others => 'Z');
|
|
|
|
-- Multiply: Operation
|
|
b_temp_sig <= sum & reg_b(31 downto 2) when b_select(9)='1' and b_select(10)='0' and b_select(11)='0' else (others => 'Z');
|
|
b_temp_sig <= sum(33 downto 2) & reg_b(47 downto 16) when b_select(10)='1' else (others => 'Z');
|
|
b_temp_sig <= sum(33 downto 2) & reg_b(55 downto 24) when b_select(11)='1' else (others => 'Z');
|
|
|
|
-- Default values
|
|
a_temp_sig <= reg_a when conv_integer(unsigned(a_select))=0 else (others => 'Z');
|
|
b_temp_sig <= reg_b when conv_integer(unsigned(b_select))=0 else (others => 'Z');
|
|
|
|
-- Result
|
|
answer_temp_sig <= ZERO when answer_select(0)='1' else
|
|
answer_reg(30 downto 0) & '1' when answer_select(1)='1' else
|
|
answer_reg(30 downto 0) & '0' when answer_select(2)='1' else
|
|
answer_reg;
|
|
|
--For Altera
|
end generate;
|
lpm_adder:
|
|
if adder_type = "ALTERA" generate
|
|
lpm_add_sub_component : lpm_add_sub
|
|
GENERIC MAP (
|
|
lpm_width => 34,
|
|
lpm_direction => "UNUSED",
|
|
lpm_type => "LPM_ADD_SUB",
|
|
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
|
|
)
|
|
PORT MAP (
|
|
dataa => aa,
|
|
add_sub => do_mult_reg,
|
|
datab => bb,
|
|
result => sum
|
|
);
|
|
end generate; --lpm_adder
|
|
|
|
end; --architecture logic
|
end; --architecture logic
|
|
|
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No newline at end of file
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No newline at end of file
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