| Line 39... |
Line 39... |
use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity mult is
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entity mult is
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generic(adder_type : string := "GENERIC";
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generic(adder_type : string := "DEFAULT";
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mult_type : string := "GENERIC");
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mult_type : string := "DEFAULT");
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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a, b : in std_logic_vector(31 downto 0);
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a, b : in std_logic_vector(31 downto 0);
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mult_func : in mult_function_type;
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mult_func : in mult_function_type;
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c_mult : out std_logic_vector(31 downto 0);
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c_mult : out std_logic_vector(31 downto 0);
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| Line 78... |
Line 78... |
signal answer_select : std_logic_vector(2 downto 0);
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signal answer_select : std_logic_vector(2 downto 0);
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begin
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begin
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--sum = aa + bb
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--sum = aa + bb
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generic_adder: if adder_type = "GENERIC" generate
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generic_adder: if adder_type = "DEFAULT" generate
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sum <= (aa + bb) when do_mult_reg = '1' else
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sum <= (aa + bb) when do_mult_reg = '1' else
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(aa - bb);
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(aa - bb);
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end generate; --generic_adder
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end generate; --generic_adder
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--For Altera: sum = aa + bb
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--For Altera: sum = aa + bb
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Line 111... |
c_mult <= reg_b(31 downto 0) when mult_func = MULT_READ_LO else
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c_mult <= reg_b(31 downto 0) when mult_func = MULT_READ_LO else
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reg_b(63 downto 32) when mult_func = MULT_READ_HI else
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reg_b(63 downto 32) when mult_func = MULT_READ_HI else
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ZERO;
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ZERO;
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GENERIC_MULT: if MULT_TYPE = "GENERIC" generate
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GENERIC_MULT: if MULT_TYPE = "DEFAULT" generate
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--multiplication/division unit
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--multiplication/division unit
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mult_proc: process(clk, reset_in, a, b, mult_func,
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mult_proc: process(clk, reset_in, a, b, mult_func,
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do_mult_reg, do_signed_reg, count_reg,
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do_mult_reg, do_signed_reg, count_reg,
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reg_a, reg_b, answer_reg, sum, reg_a_times3)
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reg_a, reg_b, answer_reg, sum, reg_a_times3)
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