| Line 32... |
Line 32... |
signal do_signed_reg : std_logic;
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signal do_signed_reg : std_logic;
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signal count_reg : std_logic_vector(5 downto 0);
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signal count_reg : std_logic_vector(5 downto 0);
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signal reg_a : std_logic_vector(31 downto 0);
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signal reg_a : std_logic_vector(31 downto 0);
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signal reg_b : std_logic_vector(63 downto 0);
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signal reg_b : std_logic_vector(63 downto 0);
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signal answer_reg : std_logic_vector(31 downto 0);
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signal answer_reg : std_logic_vector(31 downto 0);
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-- signal sum_out : std_logic_vector(32 downto 0);
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begin
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begin
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--multiplication/division unit
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--multiplication/division unit
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mult_proc: process(clk, a, b, mult_func,
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mult_proc: process(clk, a, b, mult_func,
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do_div_reg, do_signed_reg, count_reg,
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do_div_reg, do_signed_reg, count_reg,
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| Line 45... |
Line 46... |
variable count_temp : std_logic_vector(5 downto 0);
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variable count_temp : std_logic_vector(5 downto 0);
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variable a_temp : std_logic_vector(31 downto 0);
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variable a_temp : std_logic_vector(31 downto 0);
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variable b_temp : std_logic_vector(63 downto 0);
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variable b_temp : std_logic_vector(63 downto 0);
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variable answer_temp : std_logic_vector(31 downto 0);
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variable answer_temp : std_logic_vector(31 downto 0);
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variable sign_extension : std_logic;
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variable aa, bb : std_logic_vector(32 downto 0);
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variable aa, bb : std_logic_vector(32 downto 0);
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variable sum : std_logic_vector(32 downto 0);
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variable sum : std_logic_vector(32 downto 0);
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variable start : std_logic;
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variable start : std_logic;
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variable do_write : std_logic;
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variable do_write : std_logic;
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variable do_hi : std_logic;
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variable do_hi : std_logic;
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Line 60... |
count_temp := count_reg;
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count_temp := count_reg;
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a_temp := reg_a;
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a_temp := reg_a;
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b_temp := reg_b;
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b_temp := reg_b;
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answer_temp := answer_reg;
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answer_temp := answer_reg;
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sign_extension := '0';
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aa := '0' & ZERO;
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aa := '0' & ZERO;
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bb := '0' & ZERO;
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bb := '0' & ZERO;
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sum := '0' & ZERO;
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sum := '0' & ZERO;
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start := '0';
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start := '0';
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do_write := '0';
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do_write := '0';
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Line 95... |
if start = '1' then
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if start = '1' then
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count_temp := "000000";
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count_temp := "000000";
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a_temp := a;
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a_temp := a;
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answer_temp := ZERO;
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answer_temp := ZERO;
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if do_div_temp = '1' then
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if do_div_temp = '1' then
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b_temp(63) := '0';
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if do_signed_temp = '0' or b(31) = '0' then
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if do_signed_temp = '0' or b(31) = '0' then
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b_temp(62 downto 31) := b;
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b_temp(62 downto 31) := b;
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else
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else
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b_temp(62 downto 31) := bv_negate(b);
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b_temp(62 downto 31) := bv_negate(b);
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a_temp := bv_negate(a);
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a_temp := bv_negate(a);
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end if;
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end if;
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b_temp(30 downto 0) := ZERO(30 downto 0);
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b_temp(30 downto 0) := ZERO(30 downto 0);
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if do_signed_temp = '1' and a(31) = b(31) then
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do_signed_temp := '0';
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end if;
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else --multiply
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else --multiply
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b_temp := ZERO & b;
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b_temp := ZERO & b;
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end if;
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end if;
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elsif do_write = '1' then
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elsif do_write = '1' then
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if do_hi = '0' then
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if do_hi = '0' then
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Line 122... |
if do_div_reg = '1' then
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if do_div_reg = '1' then
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bb := reg_b(32 downto 0);
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bb := reg_b(32 downto 0);
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else
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else
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bb := '0' & reg_b(63 downto 32);
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bb := '0' & reg_b(63 downto 32);
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end if;
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end if;
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sign_extension := reg_a(31) and do_signed_reg;
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aa := do_signed_reg & reg_a;
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aa := sign_extension & reg_a;
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sum := bv_adder(aa, bb, do_div_reg);
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sum := bv_adder(aa, bb, do_div_reg);
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-- sum := bv_adder_lookahead(aa, bb, do_div_reg);
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-- sum := bv_adder_lookahead(aa, bb, do_div_reg);
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if count_reg(5) = '0' and start = '0' then
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if count_reg(5) = '0' and start = '0' then
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count_temp := bv_inc6(count_reg);
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count_temp := bv_inc6(count_reg);
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if do_div_reg = '1' then
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if do_div_reg = '1' then
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answer_temp(31 downto 1) := answer_reg(30 downto 0);
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answer_temp(31 downto 1) := answer_reg(30 downto 0);
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if reg_b(63 downto 32) = ZERO and sum(32) = '0' then
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if reg_b(63 downto 32) = ZERO and sum(32) = do_signed_reg then
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a_temp := sum(31 downto 0); --aa=aa-bb;
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a_temp := sum(31 downto 0); --aa=aa-bb;
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answer_temp(0) := '1';
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answer_temp(0) := '1';
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else
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else
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answer_temp(0) := '0';
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answer_temp(0) := '0';
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end if;
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end if;
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Line 184... |
c_mult <= reg_b(63 downto 32);
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c_mult <= reg_b(63 downto 32);
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else
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else
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c_mult <= ZERO;
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c_mult <= ZERO;
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end if;
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end if;
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-- sum_out <= sum;
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end process;
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end process;
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end; --architecture logic
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end; --architecture logic
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