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[/] [mlite/] [trunk/] [vhdl/] [mult.vhd] - Diff between revs 196 and 345
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| Rev 196 |
Rev 345 |
| Line 170... |
Line 170... |
lower_reg <= sum(0) & lower_reg(31 downto 1);
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lower_reg <= sum(0) & lower_reg(31 downto 1);
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sign2_reg <= sign2_reg or sign_reg;
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sign2_reg <= sign2_reg or sign_reg;
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sign_reg <= '0';
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sign_reg <= '0';
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bb_reg <= '0' & bb_reg(31 downto 1);
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bb_reg <= '0' & bb_reg(31 downto 1);
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-- The following six lines are optional for speedup
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-- The following six lines are optional for speedup
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elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
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--elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
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count_reg(5 downto 2) /= "0000" then
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-- count_reg(5 downto 2) /= "0000" then
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upper_reg <= "0000" & upper_reg(31 downto 4);
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-- upper_reg <= "0000" & upper_reg(31 downto 4);
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lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
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-- lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
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count := "100";
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-- count := "100";
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bb_reg <= "0000" & bb_reg(31 downto 4);
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-- bb_reg <= "0000" & bb_reg(31 downto 4);
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else
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else
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upper_reg <= sign2_reg & upper_reg(31 downto 1);
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upper_reg <= sign2_reg & upper_reg(31 downto 1);
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lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
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lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
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bb_reg <= '0' & bb_reg(31 downto 1);
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bb_reg <= '0' & bb_reg(31 downto 1);
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end if;
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end if;
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