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-- TITLE: Multiplication and Division Unit

-- TITLE: Multiplication and Division Unit

-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)

-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)

-- DATE CREATED: 1/31/01

-- DATE CREATED: 1/31/01

-- FILENAME: mult.vhd

-- FILENAME: mult.vhd

-- COPYRIGHT: Software placed into the public domain by the author.

-- COPYRIGHT: Software placed into the public domain by the author.

--    Software 'as is' without warranty.  Author liable for nothing.

--    Software 'as is' without warranty.  Author liable for nothing.

-- DESCRIPTION:

-- DESCRIPTION:

--    Implements the multiplication and division unit.

--    Implements the multiplication and division unit.

--    Normally takes 32 clock cycles.

--    Normally takes 32 clock cycles.

--    if b(31 downto 16) = ZERO(31 downto 16) then mult in 16 cycles. 

--    if b(31 downto 16) = ZERO(31 downto 16) then mult in 16 cycles. 

--    if b(31 downto 8) = ZERO(31 downto 8) then mult in 8 cycles. 

--    if b(31 downto 8) = ZERO(31 downto 8) then mult in 8 cycles. 

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library ieee;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_1164.all;

entity mult is

entity mult is

   port(clk       : in std_logic;

   port(clk       : in std_logic;

        a, b      : in std_logic_vector(31 downto 0);

        a, b      : in std_logic_vector(31 downto 0);

        mult_func : in mult_function_type;

        mult_func : in mult_function_type;