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[/] [mlite/] [trunk/] [vhdl/] [mult.vhd] - Diff between revs 2 and 7

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Rev 2 Rev 7
Line 7... Line 7...
-- COPYRIGHT: Software placed into the public domain by the author.
-- COPYRIGHT: Software placed into the public domain by the author.
--    Software 'as is' without warranty.  Author liable for nothing.
--    Software 'as is' without warranty.  Author liable for nothing.
-- DESCRIPTION:
-- DESCRIPTION:
--    Implements the multiplication and division unit.
--    Implements the multiplication and division unit.
--    Normally takes 32 clock cycles.
--    Normally takes 32 clock cycles.
 
--    if b(31 downto 16) = ZERO(31 downto 16) then mult in 16 cycles. 
 
--    if b(31 downto 8) = ZERO(31 downto 8) then mult in 8 cycles. 
---------------------------------------------------------------------
---------------------------------------------------------------------
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use work.mips_pack.all;
use work.mips_pack.all;
 
 
Line 102... Line 104...
            b_temp(62 downto 31) := bv_negate(b);
            b_temp(62 downto 31) := bv_negate(b);
            a_temp := bv_negate(a);
            a_temp := bv_negate(a);
         end if;
         end if;
         b_temp(30 downto 0) := ZERO(30 downto 0);
         b_temp(30 downto 0) := ZERO(30 downto 0);
      else --multiply
      else --multiply
         b_temp := zero & b;
         b_temp := ZERO & b;
      end if;
      end if;
   elsif do_write = '1' then
   elsif do_write = '1' then
      if do_hi = '0' then
      if do_hi = '0' then
         b_temp(31 downto 0) := a;
         b_temp(31 downto 0) := a;
      else
      else
Line 146... Line 148...
         else
         else
            b_temp(63 downto 31) := '0' & reg_b(63 downto 32);
            b_temp(63 downto 31) := '0' & reg_b(63 downto 32);
         end if;
         end if;
         b_temp(30 downto 0) := reg_b(31 downto 1);
         b_temp(30 downto 0) := reg_b(31 downto 1);
         if count_reg = "010000" and          --early stop
         if count_reg = "010000" and          --early stop
               reg_b(15 downto 0) = zero(15 downto 0) then
               reg_b(15 downto 0) = ZERO(15 downto 0) then
            count_temp := "111111";
            count_temp := "111111";
            b_temp(31 downto 0) := reg_b(47 downto 16);
            b_temp(31 downto 0) := reg_b(47 downto 16);
         end if;
         end if;
 
         if count_reg = "001000" and          --early stop
 
               reg_b(23 downto 0) = ZERO(23 downto 0) then
 
            count_temp := "111111";
 
            b_temp(31 downto 0) := reg_b(55 downto 24);
 
         end if;
      end if;
      end if;
   end if;
   end if;
 
 
   if rising_edge(clk) then
   if rising_edge(clk) then
      do_div_reg <= do_div_temp;
      do_div_reg <= do_div_temp;
Line 172... Line 179...
   if mult_func = mult_read_lo then
   if mult_func = mult_read_lo then
      c_mult <= reg_b(31 downto 0);
      c_mult <= reg_b(31 downto 0);
   elsif mult_func = mult_read_hi then
   elsif mult_func = mult_read_hi then
      c_mult <= reg_b(63 downto 32);
      c_mult <= reg_b(63 downto 32);
   else
   else
--      c_mult <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
 
      c_mult <= ZERO;
      c_mult <= ZERO;
   end if;
   end if;
 
 
end process;
end process;
 
 

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