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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Implements the multiplication and division unit.
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-- Implements the multiplication and division unit.
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-- Normally takes 32 clock cycles.
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-- Division takes 32 clock cycles.
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-- if b(31 downto 16) = ZERO(31 downto 16) then mult in 16 cycles.
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-- Multiplication normally takes 16 clock cycles.
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-- if b(31 downto 8) = ZERO(31 downto 8) then mult in 8 cycles.
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-- if b <= 0xffff then mult in 8 cycles.
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-- if b <= 0xff then mult in 4 cycles.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity mult is
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entity mult is
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generic(adder_type : string := "GENERIC");
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generic(adder_type : string := "GENERIC");
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port(clk : in std_logic;
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port(clk : in std_logic;
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signal do_signed_reg : std_logic;
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signal do_signed_reg : std_logic;
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signal count_reg : std_logic_vector(5 downto 0);
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signal count_reg : std_logic_vector(5 downto 0);
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signal reg_a : std_logic_vector(31 downto 0);
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signal reg_a : std_logic_vector(31 downto 0);
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signal reg_b : std_logic_vector(63 downto 0);
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signal reg_b : std_logic_vector(63 downto 0);
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signal answer_reg : std_logic_vector(31 downto 0);
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signal answer_reg : std_logic_vector(31 downto 0);
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signal aa, bb : std_logic_vector(32 downto 0);
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signal aa, bb : std_logic_vector(33 downto 0);
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signal sum : std_logic_vector(32 downto 0);
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signal sum : std_logic_vector(33 downto 0);
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signal reg_a_times3 : std_logic_vector(33 downto 0);
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begin
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begin
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--multiplication/division unit
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--multiplication/division unit
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mult_proc: process(clk, a, b, mult_func,
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mult_proc: process(clk, a, b, mult_func,
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do_mult_reg, do_signed_reg, count_reg,
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do_mult_reg, do_signed_reg, count_reg,
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reg_a, reg_b, answer_reg, sum)
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reg_a, reg_b, answer_reg, sum, reg_a_times3)
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variable do_mult_temp : std_logic;
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variable do_mult_temp : std_logic;
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variable do_signed_temp : std_logic;
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variable do_signed_temp : std_logic;
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variable count_temp : std_logic_vector(5 downto 0);
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variable count_temp : std_logic_vector(5 downto 0);
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variable a_temp : std_logic_vector(31 downto 0);
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variable a_temp : std_logic_vector(31 downto 0);
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variable b_temp : std_logic_vector(63 downto 0);
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variable b_temp : std_logic_vector(63 downto 0);
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else
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else
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b_temp(63 downto 32) := a;
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b_temp(63 downto 32) := a;
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end if;
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end if;
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end if;
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end if;
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if do_mult_reg = '0' then
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if do_mult_reg = '0' then --division
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bb <= reg_b(32 downto 0);
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aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;
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else
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bb <= reg_b(33 downto 0);
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bb <= (reg_b(63) and sign_extend) & reg_b(63 downto 32);
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else --multiplication two-bits at a time
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case reg_b(1 downto 0) is
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when "00" =>
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aa <= "00" & ZERO;
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when "01" =>
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aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;
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when "10" =>
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aa <= (reg_a(31) and sign_extend) & reg_a & '0';
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when others =>
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aa <= reg_a_times3;
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end case;
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bb <= (reg_b(63) and sign_extend) & (reg_b(63) and sign_extend) & reg_b(63 downto 32);
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end if;
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end if;
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aa <= (reg_a(31) and sign_extend) & reg_a;
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-- Choose bv_adder or lpm_add_sub
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-- sum <= bv_adder(aa, bb, do_mult_reg);
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if count_reg(5) = '0' and start = '0' then
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if count_reg(5) = '0' and start = '0' then
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count_temp := bv_inc6(count_reg);
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count_temp := bv_inc6(count_reg);
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if do_mult_reg = '0' then
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if do_mult_reg = '0' then --division
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answer_temp(31 downto 1) := answer_reg(30 downto 0);
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answer_temp(31 downto 1) := answer_reg(30 downto 0);
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if reg_b(63 downto 32) = ZERO and sum(32) = '0' then
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if reg_b(63 downto 32) = ZERO and sum(32) = '0' then
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a_temp := sum(31 downto 0); --aa=aa-bb;
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a_temp := sum(31 downto 0); --aa=aa-bb;
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answer_temp(0) := '1';
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answer_temp(0) := '1';
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else
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else
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answer_temp(0) := '0';
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answer_temp(0) := '0';
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end if;
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end if;
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if count_reg /= "011111" then
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if count_reg /= "011111" then
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b_temp(62 downto 0) := reg_b(63 downto 1);
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b_temp(62 downto 0) := reg_b(63 downto 1);
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else
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else --done with divide
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b_temp(63 downto 32) := a_temp;
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b_temp(63 downto 32) := a_temp;
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if do_signed_reg = '0' then
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if do_signed_reg = '0' then
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b_temp(31 downto 0) := answer_temp;
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b_temp(31 downto 0) := answer_temp;
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else
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else
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b_temp(31 downto 0) := bv_negate(answer_temp);
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b_temp(31 downto 0) := bv_negate(answer_temp);
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end if;
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end if;
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end if;
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end if;
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else -- mult_mode
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else -- mult_mode
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if reg_b(0) = '1' then
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b_temp(63 downto 30) := sum;
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b_temp(63 downto 31) := sum;
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b_temp(29 downto 0) := reg_b(31 downto 2);
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else
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if count_reg = "001000" and sign_extend = '0' and --early stop
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b_temp(63 downto 31) := sign_extend & reg_b(63 downto 32);
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if reg_b(63 downto 32) = ZERO then
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b_temp(63) := '0';
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end if;
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end if;
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b_temp(30 downto 0) := reg_b(31 downto 1);
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if count_reg = "010000" and sign_extend = '0' and --early stop
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reg_b(15 downto 0) = ZERO(15 downto 0) then
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reg_b(15 downto 0) = ZERO(15 downto 0) then
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count_temp := "111111";
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count_temp := "111111";
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b_temp(31 downto 0) := reg_b(47 downto 16);
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b_temp(31 downto 0) := reg_b(47 downto 16);
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end if;
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end if;
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if count_reg = "001000" and sign_extend = '0' and --early stop
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if count_reg = "000100" and sign_extend = '0' and --early stop
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reg_b(23 downto 0) = ZERO(23 downto 0) then
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reg_b(23 downto 0) = ZERO(23 downto 0) then
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count_temp := "111111";
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count_temp := "111111";
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b_temp(31 downto 0) := reg_b(55 downto 24);
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b_temp(31 downto 0) := reg_b(55 downto 24);
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end if;
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end if;
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count_temp(5) := count_temp(4);
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end if;
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end if;
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end if;
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end if;
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if rising_edge(clk) then
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if rising_edge(clk) then
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do_mult_reg <= do_mult_temp;
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do_mult_reg <= do_mult_temp;
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do_signed_reg <= do_signed_temp;
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do_signed_reg <= do_signed_temp;
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count_reg <= count_temp;
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count_reg <= count_temp;
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reg_a <= a_temp;
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reg_a <= a_temp;
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reg_b <= b_temp;
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reg_b <= b_temp;
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answer_reg <= answer_temp;
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answer_reg <= answer_temp;
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if start = '1' then
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reg_a_times3 <= ((a(31) and do_signed_temp) & a & '0') +
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((a(31) and do_signed_temp) & (a(31) and do_signed_temp) & a);
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end if;
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end if;
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end if;
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if count_reg(5) = '0' and mult_func/= mult_nothing and start = '0' then
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if count_reg(5) = '0' and mult_func/= mult_nothing and start = '0' then
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pause_out <= '1';
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pause_out <= '1';
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else
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else
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end process;
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end process;
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generic_adder:
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generic_adder:
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if adder_type /= "ALTERA" generate
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if adder_type /= "ALTERA" generate
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sum <= bv_adder(aa, bb, do_mult_reg);
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sum <= (aa + bb) when do_mult_reg = '1' else
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(aa - bb);
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end generate; --generic_adder
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end generate; --generic_adder
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--For Altera
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--For Altera
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lpm_adder:
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lpm_adder:
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if adder_type = "ALTERA" generate
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if adder_type = "ALTERA" generate
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lpm_add_sub_component : lpm_add_sub
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lpm_add_sub_component : lpm_add_sub
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GENERIC MAP (
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GENERIC MAP (
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lpm_width => 33,
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lpm_width => 34,
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lpm_direction => "UNUSED",
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lpm_direction => "UNUSED",
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lpm_type => "LPM_ADD_SUB",
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lpm_type => "LPM_ADD_SUB",
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lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
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lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
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)
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)
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PORT MAP (
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PORT MAP (
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