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[/] [mlite/] [trunk/] [vhdl/] [mult.vhd] - Diff between revs 90 and 97
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Rev 97 |
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-- Implements the multiplication and division unit.
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-- Implements the multiplication and division unit.
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-- Division takes 32 clock cycles.
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-- Division takes 32 clock cycles.
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-- Multiplication normally takes 16 clock cycles.
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-- Multiplication normally takes 16 clock cycles.
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-- if b <= 0xffff then mult in 8 cycles.
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-- if b <= 0xffff then mult in 8 cycles.
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-- if b <= 0xff then mult in 4 cycles.
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-- if b <= 0xff then mult in 4 cycles.
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--
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-- For multiplication set reg_b = 0x00000000 & b. The 64-bit result
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-- will be in reg_b. The lower bits of reg_b contain the upper
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-- bits of b that have not yet been multiplied. For 16 clock cycles
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-- shift reg_b two bits to the right. Use the lowest two bits of reg_b
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-- to multiply by two bits at a time and add the result to the upper
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-- 32-bits of reg_b (using C syntax):
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-- reg_b = (reg_b >> 2) + (((reg_b & 3) * reg_a) << 32);
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--
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-- For division set reg_b = '0' & b & 30_ZEROS. The answer will be
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-- in answer_reg and the remainder in reg_a. For 32 clock cycles
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-- (using C syntax):
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-- answer_reg = (answer_reg << 1);
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-- if (reg_a >= reg_b) {
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-- answer_reg += 1;
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-- reg_a -= reg_b;
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-- }
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-- reg_b = reg_b >> 1;
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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