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Line 19... |
pc_new : in std_logic_vector(31 downto 2);
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pc_new : in std_logic_vector(31 downto 2);
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take_branch : in std_logic;
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take_branch : in std_logic;
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pause_in : in std_logic;
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pause_in : in std_logic;
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opcode25_0 : in std_logic_vector(25 downto 0);
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opcode25_0 : in std_logic_vector(25 downto 0);
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pc_source : in pc_source_type;
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pc_source : in pc_source_type;
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pc_out : out std_logic_vector(31 downto 0);
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pc_future : out std_logic_vector(31 downto 2);
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pc_out_plus4 : out std_logic_vector(31 downto 0));
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pc_current : out std_logic_vector(31 downto 2);
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pc_plus4 : out std_logic_vector(31 downto 2));
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end; --pc_next
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end; --pc_next
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architecture logic of pc_next is
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architecture logic of pc_next is
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signal pc_reg : std_logic_vector(31 downto 2);
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signal pc_reg : std_logic_vector(31 downto 2);
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begin
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begin
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pc_next: process(clk, reset_in, pc_new, take_branch, pause_in,
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pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
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opcode25_0, pc_source, pc_reg)
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opcode25_0, pc_source, pc_reg)
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variable pc_inc, pc_next : std_logic_vector(31 downto 2);
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variable pc_inc : std_logic_vector(31 downto 2);
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variable pc_next : std_logic_vector(31 downto 2);
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begin
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begin
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pc_inc := bv_increment(pc_reg); --pc_reg+1
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pc_inc := bv_increment(pc_reg); --pc_reg+1
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case pc_source is
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case pc_source is
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when FROM_INC4 =>
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when FROM_INC4 =>
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Line 56... |
pc_next := pc_reg;
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pc_next := pc_reg;
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end if;
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end if;
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if reset_in = '1' then
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if reset_in = '1' then
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pc_reg <= ZERO(31 downto 2);
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pc_reg <= ZERO(31 downto 2);
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pc_next := pc_reg;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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pc_reg <= pc_next;
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pc_reg <= pc_next;
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end if;
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end if;
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pc_out <= pc_reg & "00";
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pc_future <= pc_next;
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pc_out_plus4 <= pc_inc & "00";
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pc_current <= pc_reg;
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pc_plus4 <= pc_inc;
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end process;
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end process;
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end; --logic
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end; --logic
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No newline at end of file
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No newline at end of file
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