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[/] [mlite/] [trunk/] [vhdl/] [pc_next.vhd] - Diff between revs 128 and 139

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Rev 128 Rev 139
Line 19... Line 19...
        pc_new       : in std_logic_vector(31 downto 2);
        pc_new       : in std_logic_vector(31 downto 2);
        take_branch  : in std_logic;
        take_branch  : in std_logic;
        pause_in     : in std_logic;
        pause_in     : in std_logic;
        opcode25_0   : in std_logic_vector(25 downto 0);
        opcode25_0   : in std_logic_vector(25 downto 0);
        pc_source    : in pc_source_type;
        pc_source    : in pc_source_type;
        pc_out       : out std_logic_vector(31 downto 0);
        pc_future   : out std_logic_vector(31 downto 2);
        pc_out_plus4 : out std_logic_vector(31 downto 0));
        pc_current  : out std_logic_vector(31 downto 2);
 
        pc_plus4    : out std_logic_vector(31 downto 2));
end; --pc_next
end; --pc_next
 
 
architecture logic of pc_next is
architecture logic of pc_next is
   signal pc_reg : std_logic_vector(31 downto 2);
   signal pc_reg : std_logic_vector(31 downto 2);
begin
begin
 
 
pc_next: process(clk, reset_in, pc_new, take_branch, pause_in,
pc_select: process(clk, reset_in, pc_new, take_branch, pause_in,
                 opcode25_0, pc_source, pc_reg)
                 opcode25_0, pc_source, pc_reg)
   variable pc_inc, pc_next : std_logic_vector(31 downto 2);
   variable pc_inc      : std_logic_vector(31 downto 2);
 
   variable pc_next : std_logic_vector(31 downto 2);
begin
begin
   pc_inc := bv_increment(pc_reg);  --pc_reg+1
   pc_inc := bv_increment(pc_reg);  --pc_reg+1
 
 
   case pc_source is
   case pc_source is
   when FROM_INC4 =>
   when FROM_INC4 =>
Line 54... Line 56...
      pc_next := pc_reg;
      pc_next := pc_reg;
   end if;
   end if;
 
 
   if reset_in = '1' then
   if reset_in = '1' then
      pc_reg <= ZERO(31 downto 2);
      pc_reg <= ZERO(31 downto 2);
 
      pc_next := pc_reg;
   elsif rising_edge(clk) then
   elsif rising_edge(clk) then
      pc_reg <= pc_next;
      pc_reg <= pc_next;
   end if;
   end if;
 
 
   pc_out <= pc_reg & "00";
   pc_future <= pc_next;
   pc_out_plus4 <= pc_inc & "00";
   pc_current <= pc_reg;
 
   pc_plus4 <= pc_inc;
end process;
end process;
 
 
end; --logic
end; --logic
 
 
 
 
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