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[/] [mlite/] [trunk/] [vhdl/] [pc_next.vhd] - Diff between revs 43 and 47

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Rev 43 Rev 47
Line 34... Line 34...
pc_next: process(clk, reset_in, pc_new, take_branch, pause_in,
pc_next: process(clk, reset_in, pc_new, take_branch, pause_in,
                 opcode25_0, pc_source, pc_reg)
                 opcode25_0, pc_source, pc_reg)
   variable pc_inc, pc_next : std_logic_vector(31 downto 2);
   variable pc_inc, pc_next : std_logic_vector(31 downto 2);
begin
begin
   pc_inc := bv_increment(pc_reg);  --pc_reg+1
   pc_inc := bv_increment(pc_reg);  --pc_reg+1
   pc_next := pc_reg;
 
   case pc_source is
   case pc_source is
   when from_inc4 =>
   when from_inc4 =>
      if pause_in = '0' then
      if pause_in = '0' then
         pc_next := pc_inc;
         pc_next := pc_inc;
 
      else
 
             pc_next := pc_reg;
      end if;
      end if;
   when from_opcode25_0 =>
   when from_opcode25_0 =>
      pc_next := pc_reg(31 downto 28) & opcode25_0;
      pc_next := pc_reg(31 downto 28) & opcode25_0;
   when from_branch | from_lbranch =>
   when others =>   --from_branch | from_lbranch =>
      if take_branch = '1' then
      if take_branch = '1' then
         pc_next := pc_new;
         pc_next := pc_new;
      else
      else
         pc_next := pc_inc;
         pc_next := pc_inc;
      end if;
      end if;
   when others =>
 
   end case;
   end case;
   if reset_in = '1' then
   if reset_in = '1' then
      pc_next := ZERO(31 downto 2);
      pc_next := ZERO(31 downto 2);
   end if;
   end if;
 
 

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