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[/] [mlite/] [trunk/] [vhdl/] [pc_next.vhd] - Diff between revs 59 and 76
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Rev 59 |
Rev 76 |
Line 34... |
Line 34... |
pc_next: process(clk, reset_in, pc_new, take_branch, pause_in,
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pc_next: process(clk, reset_in, pc_new, take_branch, pause_in,
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opcode25_0, pc_source, pc_reg)
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opcode25_0, pc_source, pc_reg)
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variable pc_inc, pc_next : std_logic_vector(31 downto 2);
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variable pc_inc, pc_next : std_logic_vector(31 downto 2);
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begin
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begin
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pc_inc := bv_increment(pc_reg); --pc_reg+1
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pc_inc := bv_increment(pc_reg); --pc_reg+1
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case pc_source is
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case pc_source is
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when from_inc4 =>
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when from_inc4 =>
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if pause_in = '0' then
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pc_next := pc_inc;
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pc_next := pc_inc;
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else
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pc_next := pc_reg;
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end if;
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when from_opcode25_0 =>
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when from_opcode25_0 =>
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pc_next := pc_reg(31 downto 28) & opcode25_0;
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pc_next := pc_reg(31 downto 28) & opcode25_0;
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when others => --from_branch | from_lbranch =>
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when others => --from_branch | from_lbranch =>
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if take_branch = '1' then
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if take_branch = '1' then
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pc_next := pc_new;
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pc_next := pc_new;
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else
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else
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pc_next := pc_inc;
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pc_next := pc_inc;
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end if;
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end if;
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end case;
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end case;
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if pause_in = '1' then
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pc_next := pc_reg;
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end if;
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if reset_in = '1' then
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if reset_in = '1' then
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pc_reg <= ZERO(31 downto 2);
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pc_reg <= ZERO(31 downto 2);
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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pc_reg <= pc_next;
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pc_reg <= pc_next;
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end if;
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end if;
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