OpenCores
URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] [pipeline.vhd] - Diff between revs 96 and 101

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 96 Rev 101
Line 59... Line 59...
      rd_index, rd_index_reg, pause_any, pause_reg,
      rd_index, rd_index_reg, pause_any, pause_reg,
      rs_index, rt_index,
      rs_index, rt_index,
      pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
      pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
      reg_dest, reg_dest_reg, c_bus)
      reg_dest, reg_dest_reg, c_bus)
   variable pause_mult_clock : std_logic;
   variable pause_mult_clock : std_logic;
 
   variable freeze_pipeline : std_logic;
begin
begin
   if (pc_source /= from_inc4 and pc_source /= from_opcode25_0) or
   if (pc_source /= from_inc4 and pc_source /= from_opcode25_0) or
      mem_source /= mem_fetch or
      mem_source /= mem_fetch or
      (mult_func = mult_read_lo or mult_func = mult_read_hi) then
      (mult_func = mult_read_lo or mult_func = mult_read_hi) then
      pause_mult_clock := '1';
      pause_mult_clock := '1';
   else
   else
      pause_mult_clock := '0';
      pause_mult_clock := '0';
   end if;
   end if;
 
 
 
   freeze_pipeline := not (pause_mult_clock and pause_reg) and pause_any;
   pause_pipeline <= pause_mult_clock and pause_reg;
   pause_pipeline <= pause_mult_clock and pause_reg;
   rd_indexD <= rd_index_reg;
   rd_indexD <= rd_index_reg;
 
 
   if c_source_reg = c_from_alu then
   if c_source_reg = c_from_alu then
      reg_destD <= c_bus;
      reg_destD <= c_bus;
   else
   else
      reg_destD <= reg_dest_reg;
      reg_destD <= reg_dest_reg;
   end if;
   end if;
 
 
   if rising_edge(clk) then
   if rising_edge(clk) and freeze_pipeline = '0' then
      if (rs_index = "000000" or rs_index /= rd_index_reg) or
      if (rs_index = "000000" or rs_index /= rd_index_reg) or
            (a_source /= a_from_reg_source or pause_reg = '0') then
            (a_source /= a_from_reg_source or pause_reg = '0') then
         a_busD <= a_bus;
         a_busD <= a_bus;
      elsif c_source_reg = c_from_alu then
      elsif c_source_reg = c_from_alu then
         a_busD <= c_bus;  --rs from previous operation (bypass stage)
         a_busD <= c_bus;  --rs from previous operation (bypass stage)
Line 112... Line 114...
      if pause_reg = '0' and pause_any = '0' then
      if pause_reg = '0' and pause_any = '0' then
         pause_reg <= '1';   --enable pause_pipeline
         pause_reg <= '1';   --enable pause_pipeline
      elsif pause_mult_clock = '1' then
      elsif pause_mult_clock = '1' then
         pause_reg <= '0';   --disable pause_pipeline
         pause_reg <= '0';   --disable pause_pipeline
      end if;
      end if;
 
      if freeze_pipeline = '0' then
      rd_index_reg <= rd_index;
      rd_index_reg <= rd_index;
   end if;
   end if;
 
   end if;
 
 
end process; --pipeline3
end process; --pipeline3
 
 
end; --logic
end; --logic
 
 
 No newline at end of file
 No newline at end of file
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.