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[/] [mlite/] [trunk/] [vhdl/] [pipeline.vhd] - Diff between revs 101 and 107

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Rev 101 Rev 107
Line 47... Line 47...
 
 
architecture logic of pipeline is
architecture logic of pipeline is
   signal rd_index_reg : std_logic_vector(5 downto 0);
   signal rd_index_reg : std_logic_vector(5 downto 0);
   signal reg_dest_reg : std_logic_vector(31 downto 0);
   signal reg_dest_reg : std_logic_vector(31 downto 0);
   signal c_source_reg : c_source_type;
   signal c_source_reg : c_source_type;
   signal pause_reg    : std_logic;
   signal pause_enable_reg : std_logic;
begin
begin
 
 
--When operating in three stage pipeline mode, the following signals
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle:  a_bus, b_bus, alu/shift/mult_func,
--are delayed by one clock cycle:  a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
      rd_index, rd_index_reg, pause_any, pause_reg,
      rd_index, rd_index_reg, pause_any, pause_enable_reg,
      rs_index, rt_index,
      rs_index, rt_index,
      pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
      pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
      reg_dest, reg_dest_reg, c_bus)
      reg_dest, reg_dest_reg, c_bus)
   variable pause_mult_clock : std_logic;
   variable pause_mult_clock : std_logic;
   variable freeze_pipeline : std_logic;
   variable freeze_pipeline : std_logic;
Line 69... Line 69...
      pause_mult_clock := '1';
      pause_mult_clock := '1';
   else
   else
      pause_mult_clock := '0';
      pause_mult_clock := '0';
   end if;
   end if;
 
 
   freeze_pipeline := not (pause_mult_clock and pause_reg) and pause_any;
   freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
   pause_pipeline <= pause_mult_clock and pause_reg;
   pause_pipeline <= pause_mult_clock and pause_enable_reg;
   rd_indexD <= rd_index_reg;
   rd_indexD <= rd_index_reg;
 
 
   if c_source_reg = c_from_alu then
   if c_source_reg = c_from_alu then
      reg_destD <= c_bus;
      reg_destD <= c_bus;
   else
   else
      reg_destD <= reg_dest_reg;
      reg_destD <= reg_dest_reg;
   end if;
   end if;
 
 
   if rising_edge(clk) and freeze_pipeline = '0' then
   if reset = '1' then
 
      pause_enable_reg <= '1';
 
      rd_index_reg <= "000000";
 
   elsif rising_edge(clk) then
 
      if freeze_pipeline = '0' then
      if (rs_index = "000000" or rs_index /= rd_index_reg) or
      if (rs_index = "000000" or rs_index /= rd_index_reg) or
            (a_source /= a_from_reg_source or pause_reg = '0') then
            (a_source /= a_from_reg_source or pause_enable_reg = '0') then
         a_busD <= a_bus;
         a_busD <= a_bus;
      elsif c_source_reg = c_from_alu then
      elsif c_source_reg = c_from_alu then
         a_busD <= c_bus;  --rs from previous operation (bypass stage)
         a_busD <= c_bus;  --rs from previous operation (bypass stage)
      else
      else
         a_busD <= reg_dest_reg;
         a_busD <= reg_dest_reg;
      end if;
      end if;
 
 
      if (rt_index = "000000" or rt_index /= rd_index_reg) or
      if (rt_index = "000000" or rt_index /= rd_index_reg) or
            (b_source /= b_from_reg_target or pause_reg = '0') then
               (b_source /= b_from_reg_target or pause_enable_reg = '0') then
         b_busD <= b_bus;
         b_busD <= b_bus;
      elsif c_source_reg = c_from_alu then
      elsif c_source_reg = c_from_alu then
         b_busD <= c_bus;  --rt from previous operation
         b_busD <= c_bus;  --rt from previous operation
      else
      else
         b_busD <= reg_dest_reg;
         b_busD <= reg_dest_reg;
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      alu_funcD <= alu_func;
      alu_funcD <= alu_func;
      shift_funcD <= shift_func;
      shift_funcD <= shift_func;
      mult_funcD <= mult_func;
      mult_funcD <= mult_func;
      reg_dest_reg <= reg_dest;
      reg_dest_reg <= reg_dest;
      c_source_reg <= c_source;
      c_source_reg <= c_source;
 
         rd_index_reg <= rd_index;
   end if;
   end if;
 
 
   if reset = '1' then
      if pause_enable_reg = '0' and pause_any = '0' then
      pause_reg <= '1';
         pause_enable_reg <= '1';   --enable pause_pipeline
      rd_index_reg <= "000000";
 
   elsif rising_edge(clk) then
 
      if pause_reg = '0' and pause_any = '0' then
 
         pause_reg <= '1';   --enable pause_pipeline
 
      elsif pause_mult_clock = '1' then
      elsif pause_mult_clock = '1' then
         pause_reg <= '0';   --disable pause_pipeline
         pause_enable_reg <= '0';   --disable pause_pipeline
      end if;
 
      if freeze_pipeline = '0' then
 
         rd_index_reg <= rd_index;
 
      end if;
      end if;
   end if;
   end if;
 
 
end process; --pipeline3
end process; --pipeline3
 
 

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