| Line 46... |
Line 46... |
end; --entity pipeline
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end; --entity pipeline
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architecture logic of pipeline is
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architecture logic of pipeline is
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signal rd_index_reg : std_logic_vector(5 downto 0);
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signal rd_index_reg : std_logic_vector(5 downto 0);
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signal reg_dest_reg : std_logic_vector(31 downto 0);
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signal reg_dest_reg : std_logic_vector(31 downto 0);
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signal reg_dest_delay : std_logic_vector(31 downto 0);
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signal c_source_reg : c_source_type;
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signal c_source_reg : c_source_type;
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signal pause_enable_reg : std_logic;
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signal pause_enable_reg : std_logic;
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begin
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begin
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|
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--When operating in three stage pipeline mode, the following signals
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--When operating in three stage pipeline mode, the following signals
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| Line 57... |
Line 58... |
--c_source, and rd_index.
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--c_source, and rd_index.
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pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
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pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
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rd_index, rd_index_reg, pause_any, pause_enable_reg,
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rd_index, rd_index_reg, pause_any, pause_enable_reg,
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rs_index, rt_index,
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rs_index, rt_index,
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pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
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pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
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reg_dest, reg_dest_reg, c_bus)
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reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
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variable pause_mult_clock : std_logic;
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variable pause_mult_clock : std_logic;
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variable freeze_pipeline : std_logic;
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variable freeze_pipeline : std_logic;
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begin
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begin
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if (pc_source /= from_inc4 and pc_source /= from_opcode25_0) or
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if (pc_source /= from_inc4 and pc_source /= from_opcode25_0) or
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mem_source /= mem_fetch or
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mem_source /= mem_fetch or
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| Line 74... |
Line 75... |
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
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freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
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pause_pipeline <= pause_mult_clock and pause_enable_reg;
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pause_pipeline <= pause_mult_clock and pause_enable_reg;
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rd_indexD <= rd_index_reg;
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rd_indexD <= rd_index_reg;
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|
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if c_source_reg = c_from_alu then
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if c_source_reg = c_from_alu then
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reg_destD <= c_bus;
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reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
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else
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else
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reg_destD <= reg_dest_reg;
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reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
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end if;
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end if;
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reg_destD <= reg_dest_delay;
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if reset = '1' then
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if reset = '1' then
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pause_enable_reg <= '1';
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pause_enable_reg <= '1';
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rd_index_reg <= "000000";
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rd_index_reg <= "000000";
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if freeze_pipeline = '0' then
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if freeze_pipeline = '0' then
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if (rs_index = "000000" or rs_index /= rd_index_reg) or
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if (rs_index = "000000" or rs_index /= rd_index_reg) or
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(a_source /= a_from_reg_source or pause_enable_reg = '0') then
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(a_source /= a_from_reg_source or pause_enable_reg = '0') then
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a_busD <= a_bus;
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a_busD <= a_bus;
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elsif c_source_reg = c_from_alu then
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a_busD <= c_bus; --rs from previous operation (bypass stage)
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else
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else
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a_busD <= reg_dest_reg;
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a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
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end if;
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end if;
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|
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if (rt_index = "000000" or rt_index /= rd_index_reg) or
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if (rt_index = "000000" or rt_index /= rd_index_reg) or
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(b_source /= b_from_reg_target or pause_enable_reg = '0') then
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(b_source /= b_from_reg_target or pause_enable_reg = '0') then
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b_busD <= b_bus;
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b_busD <= b_bus;
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elsif c_source_reg = c_from_alu then
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b_busD <= c_bus; --rt from previous operation
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else
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else
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b_busD <= reg_dest_reg;
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b_busD <= reg_dest_delay; --rt from previous operation
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end if;
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end if;
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|
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alu_funcD <= alu_func;
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alu_funcD <= alu_func;
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shift_funcD <= shift_func;
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shift_funcD <= shift_func;
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mult_funcD <= mult_func;
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mult_funcD <= mult_func;
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