| Line 62... |
Line 62... |
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
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pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
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reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
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reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
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variable pause_mult_clock : std_logic;
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variable pause_mult_clock : std_logic;
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variable freeze_pipeline : std_logic;
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variable freeze_pipeline : std_logic;
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begin
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begin
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if (pc_source /= from_inc4 and pc_source /= from_opcode25_0) or
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if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
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mem_source /= mem_fetch or
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mem_source /= MEM_FETCH or
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(mult_func = mult_read_lo or mult_func = mult_read_hi) then
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(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
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pause_mult_clock := '1';
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pause_mult_clock := '1';
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else
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else
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pause_mult_clock := '0';
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pause_mult_clock := '0';
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end if;
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end if;
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freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
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freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
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pause_pipeline <= pause_mult_clock and pause_enable_reg;
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pause_pipeline <= pause_mult_clock and pause_enable_reg;
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rd_indexD <= rd_index_reg;
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rd_indexD <= rd_index_reg;
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if c_source_reg = c_from_alu then
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if c_source_reg = C_FROM_ALU then
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reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
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reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
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else
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else
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reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
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reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
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end if;
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end if;
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reg_destD <= reg_dest_delay;
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reg_destD <= reg_dest_delay;
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if reset = '1' then
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if reset = '1' then
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pause_enable_reg <= '1';
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a_busD <= ZERO;
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b_busD <= ZERO;
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alu_funcD <= ALU_NOTHING;
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shift_funcD <= SHIFT_NOTHING;
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mult_funcD <= MULT_NOTHING;
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reg_dest_reg <= ZERO;
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c_source_reg <= "000";
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rd_index_reg <= "000000";
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rd_index_reg <= "000000";
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pause_enable_reg <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if freeze_pipeline = '0' then
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if freeze_pipeline = '0' then
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if (rs_index = "000000" or rs_index /= rd_index_reg) or
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if (rs_index = "000000" or rs_index /= rd_index_reg) or
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(a_source /= a_from_reg_source or pause_enable_reg = '0') then
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(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
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a_busD <= a_bus;
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a_busD <= a_bus;
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else
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else
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a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
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a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
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end if;
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end if;
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if (rt_index = "000000" or rt_index /= rd_index_reg) or
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if (rt_index = "000000" or rt_index /= rd_index_reg) or
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(b_source /= b_from_reg_target or pause_enable_reg = '0') then
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(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
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b_busD <= b_bus;
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b_busD <= b_bus;
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else
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else
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b_busD <= reg_dest_delay; --rt from previous operation
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b_busD <= reg_dest_delay; --rt from previous operation
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end if;
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end if;
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