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[/] [mlite/] [trunk/] [vhdl/] [pipeline.vhd] - Diff between revs 139 and 204

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Rev 139 Rev 204
Line 74... Line 74...
 
 
   freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
   freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
   pause_pipeline <= pause_mult_clock and pause_enable_reg;
   pause_pipeline <= pause_mult_clock and pause_enable_reg;
   rd_indexD <= rd_index_reg;
   rd_indexD <= rd_index_reg;
 
 
 
   -- The value written back into the register bank, signal reg_dest is tricky.
 
   -- If reg_dest comes from the ALU via the signal c_bus, it is already delayed 
 
   -- into stage #3, because a_busD and b_busD are delayed.  If reg_dest comes from 
 
   -- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into 
 
   -- stage #3.
 
   -- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
 
   -- are multiplexed into reg_dest which is then delayed.  The decision to use
 
   -- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is 
 
   -- based on a delayed value of c_source (c_source_reg).
 
 
   if c_source_reg = C_FROM_ALU then
   if c_source_reg = C_FROM_ALU then
      reg_dest_delay <= c_bus;        --delayed by 1 clock cycle via a_busD & b_busD
      reg_dest_delay <= c_bus;        --delayed by 1 clock cycle via a_busD & b_busD
   else
   else
      reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
      reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
   end if;
   end if;

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