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[/] [mlite/] [trunk/] [vhdl/] [pipeline.vhd] - Diff between revs 139 and 204
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Rev 139 |
Rev 204 |
Line 74... |
Line 74... |
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freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
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freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
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pause_pipeline <= pause_mult_clock and pause_enable_reg;
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pause_pipeline <= pause_mult_clock and pause_enable_reg;
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rd_indexD <= rd_index_reg;
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rd_indexD <= rd_index_reg;
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-- The value written back into the register bank, signal reg_dest is tricky.
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-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
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-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
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-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
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-- stage #3.
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-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
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-- are multiplexed into reg_dest which is then delayed. The decision to use
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-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
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-- based on a delayed value of c_source (c_source_reg).
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if c_source_reg = C_FROM_ALU then
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if c_source_reg = C_FROM_ALU then
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reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
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reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
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else
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else
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reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
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reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
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end if;
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end if;
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