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Line 58... |
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
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--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
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--c_source, and rd_index.
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--c_source, and rd_index.
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pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
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pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
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rd_index, rd_index_reg, pause_any, pause_reg,
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rd_index, rd_index_reg, pause_any, pause_reg,
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take_branch, rs_index, rt_index,
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take_branch, rs_index, rt_index,
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pc_source, mem_source, c_source, c_source_reg,
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pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
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reg_dest, reg_dest_reg)
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reg_dest, reg_dest_reg, c_bus)
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variable pause_mult_clock : std_logic;
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variable pause_mult_clock : std_logic;
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begin
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begin
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if (pc_source /= from_inc4 and pc_source /= from_opcode25_0) or
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if (pc_source /= from_inc4 and pc_source /= from_opcode25_0) or
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mem_source /= mem_fetch or
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mem_source /= mem_fetch or
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(mult_func = mult_read_lo or mult_func = mult_read_hi) then
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(mult_func = mult_read_lo or mult_func = mult_read_hi) then
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