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        mem_source     : in  mem_source_type;

        mem_source     : in  mem_source_type;

        a_source       : in  a_source_type;

        a_source       : in  a_source_type;

        b_source       : in  b_source_type;

        b_source       : in  b_source_type;

        c_source       : in  c_source_type;

        c_source       : in  c_source_type;

        c_bus          : in  std_logic_vector(31 downto 0);

        c_bus          : in  std_logic_vector(31 downto 0);

        pause_any      : in  std_logic;

        pause_any      : in  std_logic;

        pause_pipeline : out std_logic);

        pause_pipeline : out std_logic);

end; --entity pipeline

end; --entity pipeline

architecture logic of pipeline is

architecture logic of pipeline is

--When operating in three stage pipeline mode, the following signals

--When operating in three stage pipeline mode, the following signals

--are delayed by one clock cycle:  a_bus, b_bus, alu/shift/mult_func,

--are delayed by one clock cycle:  a_bus, b_bus, alu/shift/mult_func,

--c_source, and rd_index.

--c_source, and rd_index.

pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,

pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,

      rd_index, rd_index_reg, pause_any, pause_reg,

      rd_index, rd_index_reg, pause_any, pause_reg,

      pc_source, mem_source, a_source, b_source, c_source, c_source_reg,

      pc_source, mem_source, a_source, b_source, c_source, c_source_reg,

      reg_dest, reg_dest_reg, c_bus)

      reg_dest, reg_dest_reg, c_bus)

   variable pause_mult_clock : std_logic;

   variable pause_mult_clock : std_logic;

begin

begin

   if (pc_source /= from_inc4 and pc_source /= from_opcode25_0) or

   if (pc_source /= from_inc4 and pc_source /= from_opcode25_0) or

   else

   else

      pause_mult_clock := '0';

      pause_mult_clock := '0';

   end if;

   end if;

   pause_pipeline <= pause_mult_clock and pause_reg;

   pause_pipeline <= pause_mult_clock and pause_reg;

   rd_indexD <= rd_index_reg;

   rd_indexD <= rd_index_reg;

   if c_source_reg = c_from_alu then

   if c_source_reg = c_from_alu then

      reg_destD <= c_bus;

      reg_destD <= c_bus;

   else

   else