| Line 15... |
Line 15... |
-- Access all Misc registers with 32-bit accesses
|
-- Access all Misc registers with 32-bit accesses
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-- 0x20000000 Uart Write (will pause CPU if busy)
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-- 0x20000000 Uart Write (will pause CPU if busy)
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-- 0x20000000 Uart Read
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-- 0x20000000 Uart Read
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-- 0x20000010 IRQ Mask
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-- 0x20000010 IRQ Mask
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-- 0x20000020 IRQ Status
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-- 0x20000020 IRQ Status
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-- 0x20000030 GPIO0 Out
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-- 0x20000030 GPIO0 Out Set bits
|
|
-- 0x20000040 GPIO0 Out Clear bits
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-- 0x20000050 GPIOA In
|
-- 0x20000050 GPIOA In
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-- 0x20000060 Counter
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-- 0x20000060 Counter
|
|
-- 0x20000070 Ethernet transmit count
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-- IRQ bits:
|
-- IRQ bits:
|
-- 7 GPIO31
|
-- 7 GPIO31
|
-- 6 GPIO30
|
-- 6 GPIO30
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-- 5 ^GPIO31
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-- 5 EthernetSendDone
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-- 4 ^GPIO30
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-- 4 EthernetReceive
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-- 3 Counter(18)
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-- 3 Counter(18)
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-- 2 ^Counter(18)
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-- 2 ^Counter(18)
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-- 1 ^UartWriteBusy
|
-- 1 ^UartWriteBusy
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-- 0 UartDataAvailable
|
-- 0 UartDataAvailable
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
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| Line 34... |
Line 36... |
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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|
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entity plasma is
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entity plasma is
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generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
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generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
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log_file : string := "UNUSED");
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log_file : string := "UNUSED";
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ethernet : std_logic := '0');
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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|
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uart_write : out std_logic;
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uart_write : out std_logic;
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uart_read : in std_logic;
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uart_read : in std_logic;
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| Line 62... |
Line 65... |
signal data_w : std_logic_vector(31 downto 0);
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signal data_w : std_logic_vector(31 downto 0);
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signal data_read_ram : std_logic_vector(31 downto 0);
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signal data_read_ram : std_logic_vector(31 downto 0);
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signal data_read_uart : std_logic_vector(7 downto 0);
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signal data_read_uart : std_logic_vector(7 downto 0);
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signal write_enable : std_logic;
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signal write_enable : std_logic;
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signal mem_pause : std_logic;
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signal mem_pause : std_logic;
|
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signal eth_pause : std_logic;
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|
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signal enable_internal_ram : std_logic;
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signal enable_internal_ram : std_logic;
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signal enable_misc : std_logic;
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signal enable_misc : std_logic;
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signal enable_uart : std_logic;
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signal enable_uart : std_logic;
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signal enable_uart_read : std_logic;
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signal enable_uart_read : std_logic;
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signal enable_uart_write : std_logic;
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signal enable_uart_write : std_logic;
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signal enable_eth : std_logic;
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|
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signal gpio0_reg : std_logic_vector(31 downto 0);
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signal gpio0_reg : std_logic_vector(31 downto 0);
|
|
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signal uart_write_busy : std_logic;
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signal uart_write_busy : std_logic;
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signal uart_data_avail : std_logic;
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signal uart_data_avail : std_logic;
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signal irq_mask_reg : std_logic_vector(7 downto 0);
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signal irq_mask_reg : std_logic_vector(7 downto 0);
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signal irq_status : std_logic_vector(7 downto 0);
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signal irq_status : std_logic_vector(7 downto 0);
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signal irq : std_logic;
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signal irq : std_logic;
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signal irq_eth_rec : std_logic;
|
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signal irq_eth_send : std_logic;
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signal counter_reg : std_logic_vector(31 downto 0);
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signal counter_reg : std_logic_vector(31 downto 0);
|
|
|
begin --architecture
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begin --architecture
|
address <= mem_address;
|
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byte_we <= mem_byte_we;
|
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data_write <= data_w;
|
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write_enable <= '1' when mem_byte_we /= "0000" else '0';
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write_enable <= '1' when mem_byte_we /= "0000" else '0';
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mem_pause <= mem_pause_in or (uart_write_busy and enable_uart and write_enable);
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mem_pause <= ((mem_pause_in or eth_pause) and not enable_misc) or
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irq_status <= gpioA_in(31 downto 30) & (gpioA_in(31 downto 30) xor "11") &
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(uart_write_busy and enable_uart and write_enable);
|
|
irq_status <= gpioA_in(31) & not gpioA_in(31) &
|
|
irq_eth_send & irq_eth_rec &
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counter_reg(18) & not counter_reg(18) &
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counter_reg(18) & not counter_reg(18) &
|
not uart_write_busy & uart_data_avail;
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not uart_write_busy & uart_data_avail;
|
irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
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irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
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gpio0_out <= gpio0_reg;
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gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
|
|
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
|
|
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enable_internal_ram <= '1' when address_next(30 downto 28) = "000" else '0';
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enable_internal_ram <= '1' when address_next(30 downto 28) = "000" else '0';
|
enable_misc <= '1' when mem_address(30 downto 28) = "010" else '0';
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enable_misc <= '1' when mem_address(30 downto 28) = "010" else '0';
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enable_uart <= '1' when enable_misc = '1' and mem_address(7 downto 4) = "0000" else '0';
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enable_uart <= '1' when enable_misc = '1' and mem_address(7 downto 4) = "0000" else '0';
|
enable_uart_read <= enable_uart and not write_enable;
|
enable_uart_read <= enable_uart and not write_enable;
|
enable_uart_write <= enable_uart and write_enable;
|
enable_uart_write <= enable_uart and write_enable;
|
|
enable_eth <= '1' when enable_misc = '1' and mem_address(7 downto 4) = "0111" else '0';
|
|
|
u1_cpu: mlite_cpu
|
u1_cpu: mlite_cpu
|
generic map (memory_type => memory_type)
|
generic map (memory_type => memory_type)
|
PORT MAP (
|
PORT MAP (
|
clk => clk,
|
clk => clk,
|
| Line 139... |
Line 147... |
when "110" => --counter
|
when "110" => --counter
|
data_r <= counter_reg;
|
data_r <= counter_reg;
|
when others =>
|
when others =>
|
data_r <= gpioA_in;
|
data_r <= gpioA_in;
|
end case;
|
end case;
|
|
when "011" => --flash
|
|
data_r <= data_read;
|
when others =>
|
when others =>
|
data_r <= ZERO;
|
data_r <= ZERO;
|
end case;
|
end case;
|
|
|
if reset = '1' then
|
if reset = '1' then
|
| Line 153... |
Line 163... |
if mem_pause = '0' then
|
if mem_pause = '0' then
|
if enable_misc = '1' and write_enable = '1' then
|
if enable_misc = '1' and write_enable = '1' then
|
if mem_address(6 downto 4) = "001" then
|
if mem_address(6 downto 4) = "001" then
|
irq_mask_reg <= data_w(7 downto 0);
|
irq_mask_reg <= data_w(7 downto 0);
|
elsif mem_address(6 downto 4) = "011" then
|
elsif mem_address(6 downto 4) = "011" then
|
gpio0_reg <= data_w;
|
gpio0_reg <= gpio0_reg or data_w;
|
|
elsif mem_address(6 downto 4) = "100" then
|
|
gpio0_reg <= gpio0_reg and not data_w;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
counter_reg <= bv_inc(counter_reg);
|
counter_reg <= bv_inc(counter_reg);
|
end if;
|
end if;
|
| Line 185... |
Line 197... |
uart_read => uart_read,
|
uart_read => uart_read,
|
uart_write => uart_write,
|
uart_write => uart_write,
|
busy_write => uart_write_busy,
|
busy_write => uart_write_busy,
|
data_avail => uart_data_avail);
|
data_avail => uart_data_avail);
|
|
|
|
dma_gen: if ethernet = '0' generate
|
|
address <= mem_address;
|
|
byte_we <= mem_byte_we;
|
|
data_write <= data_w;
|
|
eth_pause <= '0';
|
|
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
|
|
irq_eth_rec <= '0';
|
|
irq_eth_send <= '0';
|
|
end generate;
|
|
|
|
dma_gen2: if ethernet = '1' generate
|
|
u4_eth: eth_dma
|
|
port map(
|
|
clk => clk,
|
|
reset => reset,
|
|
enable_eth => gpio0_reg(24),
|
|
select_eth => enable_eth,
|
|
rec_isr => irq_eth_rec,
|
|
send_isr => irq_eth_send,
|
|
|
|
address => address, --to DDR
|
|
byte_we => byte_we,
|
|
data_write => data_write,
|
|
data_read => data_read,
|
|
pause_in => mem_pause_in,
|
|
|
|
mem_address => mem_address, --from CPU
|
|
mem_byte_we => mem_byte_we,
|
|
data_w => data_w,
|
|
pause_out => eth_pause,
|
|
|
|
E_RX_CLK => gpioA_in(20),
|
|
E_RX_DV => gpioA_in(19),
|
|
E_RXD => gpioA_in(18 downto 15),
|
|
E_TX_CLK => gpioA_in(14),
|
|
E_TX_EN => gpio0_out(28),
|
|
E_TXD => gpio0_out(27 downto 24));
|
|
end generate;
|
|
|
end; --architecture logic
|
end; --architecture logic
|
|
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No newline at end of file
|
No newline at end of file
|
