| Line 37... |
Line 37... |
use work.mlite_pack.all;
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use work.mlite_pack.all;
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|
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entity plasma is
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entity plasma is
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generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
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generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
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log_file : string := "UNUSED";
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log_file : string := "UNUSED";
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ethernet : std_logic := '0');
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ethernet : std_logic := '0';
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use_cache : std_logic := '0');
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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uart_write : out std_logic;
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uart_write : out std_logic;
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uart_read : in std_logic;
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uart_read : in std_logic;
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| Line 49... |
Line 50... |
address : out std_logic_vector(31 downto 2);
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address : out std_logic_vector(31 downto 2);
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byte_we : out std_logic_vector(3 downto 0);
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byte_we : out std_logic_vector(3 downto 0);
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data_write : out std_logic_vector(31 downto 0);
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data_write : out std_logic_vector(31 downto 0);
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data_read : in std_logic_vector(31 downto 0);
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data_read : in std_logic_vector(31 downto 0);
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mem_pause_in : in std_logic;
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mem_pause_in : in std_logic;
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no_ddr_start : out std_logic;
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no_ddr_stop : out std_logic;
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gpio0_out : out std_logic_vector(31 downto 0);
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gpio0_out : out std_logic_vector(31 downto 0);
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gpioA_in : in std_logic_vector(31 downto 0));
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gpioA_in : in std_logic_vector(31 downto 0));
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end; --entity plasma
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end; --entity plasma
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architecture logic of plasma is
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architecture logic of plasma is
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signal address_next : std_logic_vector(31 downto 2);
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signal address_next : std_logic_vector(31 downto 2);
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signal byte_we_next : std_logic_vector(3 downto 0);
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signal byte_we_next : std_logic_vector(3 downto 0);
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signal mem_address : std_logic_vector(31 downto 2);
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signal cpu_address : std_logic_vector(31 downto 0);
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signal mem_byte_we : std_logic_vector(3 downto 0);
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal data_r : std_logic_vector(31 downto 0);
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signal cpu_data_w : std_logic_vector(31 downto 0);
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signal data_w : std_logic_vector(31 downto 0);
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signal cpu_data_r : std_logic_vector(31 downto 0);
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signal data_read_ram : std_logic_vector(31 downto 0);
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signal cpu_pause : std_logic;
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signal data_read_uart : std_logic_vector(7 downto 0);
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signal data_read_uart : std_logic_vector(7 downto 0);
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signal write_enable : std_logic;
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signal write_enable : std_logic;
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signal mem_pause : std_logic;
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signal eth_pause_in : std_logic;
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signal eth_pause : std_logic;
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signal eth_pause : std_logic;
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signal mem_busy : std_logic;
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signal enable_internal_ram : std_logic;
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signal enable_misc : std_logic;
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signal enable_misc : std_logic;
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signal enable_uart : std_logic;
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signal enable_uart : std_logic;
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signal enable_uart_read : std_logic;
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signal enable_uart_read : std_logic;
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signal enable_uart_write : std_logic;
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signal enable_uart_write : std_logic;
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signal enable_eth : std_logic;
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signal enable_eth : std_logic;
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signal gpio0_reg : std_logic_vector(31 downto 0);
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signal gpio0_reg : std_logic_vector(31 downto 0);
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signal uart_write_busy : std_logic;
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signal uart_write_busy : std_logic;
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signal uart_data_avail : std_logic;
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signal uart_data_avail : std_logic;
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signal irq_mask_reg : std_logic_vector(7 downto 0);
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signal irq_mask_reg : std_logic_vector(7 downto 0);
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signal irq_status : std_logic_vector(7 downto 0);
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signal irq_status : std_logic_vector(7 downto 0);
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signal irq : std_logic;
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signal irq : std_logic;
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signal irq_eth_rec : std_logic;
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signal irq_eth_rec : std_logic;
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signal irq_eth_send : std_logic;
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signal irq_eth_send : std_logic;
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signal counter_reg : std_logic_vector(31 downto 0);
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signal counter_reg : std_logic_vector(31 downto 0);
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signal ram_enable : std_logic;
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signal ram_byte_we : std_logic_vector(3 downto 0);
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signal ram_address : std_logic_vector(31 downto 2);
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signal ram_data_w : std_logic_vector(31 downto 0);
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signal ram_data_r : std_logic_vector(31 downto 0);
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signal cache_check : std_logic;
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signal cache_checking : std_logic;
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signal cache_miss : std_logic;
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signal cache_hit : std_logic;
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begin --architecture
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begin --architecture
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write_enable <= '1' when mem_byte_we /= "0000" else '0';
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write_enable <= '1' when cpu_byte_we /= "0000" else '0';
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mem_pause <= ((mem_pause_in or eth_pause) and not enable_misc) or
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mem_busy <= eth_pause or mem_pause_in;
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(uart_write_busy and enable_uart and write_enable);
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cache_hit <= cache_checking and not cache_miss;
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cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
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cache_miss or --Cache wait
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(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash --DDR in use
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irq_status <= gpioA_in(31) & not gpioA_in(31) &
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irq_status <= gpioA_in(31) & not gpioA_in(31) &
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irq_eth_send & irq_eth_rec &
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irq_eth_send & irq_eth_rec &
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counter_reg(18) & not counter_reg(18) &
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counter_reg(18) & not counter_reg(18) &
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not uart_write_busy & uart_data_avail;
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not uart_write_busy & uart_data_avail;
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irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
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irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
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gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
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gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
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gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
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gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
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enable_internal_ram <= '1' when address_next(30 downto 28) = "000" else '0';
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enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
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enable_misc <= '1' when mem_address(30 downto 28) = "010" else '0';
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enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
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enable_uart <= '1' when enable_misc = '1' and mem_address(7 downto 4) = "0000" else '0';
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enable_uart_read <= enable_uart and not write_enable;
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enable_uart_read <= enable_uart and not write_enable;
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enable_uart_write <= enable_uart and write_enable;
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enable_uart_write <= enable_uart and write_enable;
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enable_eth <= '1' when enable_misc = '1' and mem_address(7 downto 4) = "0111" else '0';
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enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
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cpu_address(1 downto 0) <= "00";
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u1_cpu: mlite_cpu
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u1_cpu: mlite_cpu
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generic map (memory_type => memory_type)
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generic map (memory_type => memory_type)
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PORT MAP (
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PORT MAP (
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clk => clk,
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clk => clk,
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reset_in => reset,
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reset_in => reset,
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intr_in => irq,
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intr_in => irq,
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address_next => address_next, --before rising_edge(clk)
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byte_we_next => byte_we_next,
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address => cpu_address(31 downto 2), --after rising_edge(clk)
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byte_we => cpu_byte_we,
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data_w => cpu_data_w,
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data_r => cpu_data_r,
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mem_pause => cpu_pause);
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opt_cache: if use_cache = '0' generate
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cache_check <= '0';
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cache_checking <= '0';
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cache_miss <= '0';
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end generate;
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opt_cache2: if use_cache = '1' generate
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--Control 4KB unified cache that uses the upper 4KB of the 8KB
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--internal RAM. Only lowest 2MB of DDR is cached.
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u_cache: cache
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generic map (memory_type => memory_type)
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PORT MAP (
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clk => clk,
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reset => reset,
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address_next => address_next,
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address_next => address_next,
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byte_we_next => byte_we_next,
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byte_we_next => byte_we_next,
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cpu_address => cpu_address(31 downto 2),
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mem_busy => mem_busy,
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address => mem_address,
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cache_check => cache_check, --Stage1: address_next in first 2MB DDR
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byte_we => mem_byte_we,
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cache_checking => cache_checking, --Stage2
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data_w => data_w,
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cache_miss => cache_miss); --Stage3
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data_r => data_r,
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end generate; --opt_cache2
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mem_pause => mem_pause);
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no_ddr_start <= not eth_pause and cache_checking;
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no_ddr_stop <= not eth_pause and cache_miss;
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eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
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misc_proc: process(clk, reset, address_next, mem_address, enable_misc,
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misc_proc: process(clk, reset, cpu_address, enable_misc,
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data_read_ram, data_read, data_read_uart, mem_pause,
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ram_data_r, data_read, data_read_uart, cpu_pause,
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irq_mask_reg, irq_status, gpio0_reg, write_enable,
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irq_mask_reg, irq_status, gpio0_reg, write_enable,
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gpioA_in, counter_reg, data_w)
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cache_checking,
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gpioA_in, counter_reg, cpu_data_w)
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begin
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begin
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case mem_address(30 downto 28) is
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case cpu_address(30 downto 28) is
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when "000" => --internal RAM
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when "000" => --internal RAM
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data_r <= data_read_ram;
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cpu_data_r <= ram_data_r;
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when "001" => --external RAM
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when "001" => --external RAM
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data_r <= data_read;
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if cache_checking = '1' then
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cpu_data_r <= ram_data_r; --cache
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else
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cpu_data_r <= data_read; --DDR
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end if;
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when "010" => --misc
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when "010" => --misc
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case mem_address(6 downto 4) is
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case cpu_address(6 downto 4) is
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when "000" => --uart
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when "000" => --uart
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data_r <= ZERO(31 downto 8) & data_read_uart;
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cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
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when "001" => --irq_mask
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when "001" => --irq_mask
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data_r <= ZERO(31 downto 8) & irq_mask_reg;
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cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
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when "010" => --irq_status
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when "010" => --irq_status
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data_r <= ZERO(31 downto 8) & irq_status;
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cpu_data_r <= ZERO(31 downto 8) & irq_status;
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when "011" => --gpio0
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when "011" => --gpio0
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data_r <= gpio0_reg;
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cpu_data_r <= gpio0_reg;
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when "101" => --gpioA
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when "101" => --gpioA
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data_r <= gpioA_in;
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cpu_data_r <= gpioA_in;
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when "110" => --counter
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when "110" => --counter
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data_r <= counter_reg;
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cpu_data_r <= counter_reg;
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when others =>
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when others =>
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data_r <= gpioA_in;
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cpu_data_r <= gpioA_in;
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end case;
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end case;
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when "011" => --flash
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when "011" => --flash
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data_r <= data_read;
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cpu_data_r <= data_read;
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when others =>
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when others =>
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data_r <= ZERO;
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cpu_data_r <= ZERO;
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end case;
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end case;
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|
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if reset = '1' then
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if reset = '1' then
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irq_mask_reg <= ZERO(7 downto 0);
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irq_mask_reg <= ZERO(7 downto 0);
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gpio0_reg <= ZERO;
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gpio0_reg <= ZERO;
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counter_reg <= ZERO;
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counter_reg <= ZERO;
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if mem_pause = '0' then
|
if cpu_pause = '0' then
|
if enable_misc = '1' and write_enable = '1' then
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if enable_misc = '1' and write_enable = '1' then
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if mem_address(6 downto 4) = "001" then
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if cpu_address(6 downto 4) = "001" then
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irq_mask_reg <= data_w(7 downto 0);
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irq_mask_reg <= cpu_data_w(7 downto 0);
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elsif mem_address(6 downto 4) = "011" then
|
elsif cpu_address(6 downto 4) = "011" then
|
gpio0_reg <= gpio0_reg or data_w;
|
gpio0_reg <= gpio0_reg or cpu_data_w;
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elsif mem_address(6 downto 4) = "100" then
|
elsif cpu_address(6 downto 4) = "100" then
|
gpio0_reg <= gpio0_reg and not data_w;
|
gpio0_reg <= gpio0_reg and not cpu_data_w;
|
end if;
|
end if;
|
end if;
|
end if;
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end if;
|
end if;
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counter_reg <= bv_inc(counter_reg);
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counter_reg <= bv_inc(counter_reg);
|
end if;
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end if;
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end process;
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end process;
|
|
|
|
ram_enable <= '1' when address_next(30 downto 28) = "000" or
|
|
cache_check = '1' or cache_miss = '1' else '0';
|
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ram_byte_we <= byte_we_next when cache_miss = '0' else "1111";
|
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ram_address(31 downto 13) <= ZERO(31 downto 13);
|
|
ram_address(12 downto 2) <= (address_next(12) or cache_check) & address_next(11 downto 2)
|
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when cache_miss = '0' else
|
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'1' & cpu_address(11 downto 2); --Update cache after cache miss
|
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ram_data_w <= cpu_data_w when cache_miss = '0' else data_read;
|
|
|
u2_ram: ram
|
u2_ram: ram
|
generic map (memory_type => memory_type)
|
generic map (memory_type => memory_type)
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port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
enable => enable_internal_ram,
|
enable => ram_enable,
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write_byte_enable => byte_we_next,
|
write_byte_enable => ram_byte_we,
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address => address_next,
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address => ram_address,
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data_write => data_w,
|
data_write => ram_data_w,
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data_read => data_read_ram);
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data_read => ram_data_r);
|
|
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u3_uart: uart
|
u3_uart: uart
|
generic map (log_file => log_file)
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generic map (log_file => log_file)
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port map(
|
port map(
|
clk => clk,
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clk => clk,
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reset => reset,
|
reset => reset,
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enable_read => enable_uart_read,
|
enable_read => enable_uart_read,
|
enable_write => enable_uart_write,
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enable_write => enable_uart_write,
|
data_in => data_w(7 downto 0),
|
data_in => cpu_data_w(7 downto 0),
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data_out => data_read_uart,
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data_out => data_read_uart,
|
uart_read => uart_read,
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uart_read => uart_read,
|
uart_write => uart_write,
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uart_write => uart_write,
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busy_write => uart_write_busy,
|
busy_write => uart_write_busy,
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data_avail => uart_data_avail);
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data_avail => uart_data_avail);
|
|
|
dma_gen: if ethernet = '0' generate
|
dma_gen: if ethernet = '0' generate
|
address <= mem_address;
|
address <= cpu_address(31 downto 2);
|
byte_we <= mem_byte_we;
|
byte_we <= cpu_byte_we;
|
data_write <= data_w;
|
data_write <= cpu_data_w;
|
eth_pause <= '0';
|
eth_pause <= '0';
|
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
|
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
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irq_eth_rec <= '0';
|
irq_eth_rec <= '0';
|
irq_eth_send <= '0';
|
irq_eth_send <= '0';
|
end generate;
|
end generate;
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| Line 221... |
Line 280... |
|
|
address => address, --to DDR
|
address => address, --to DDR
|
byte_we => byte_we,
|
byte_we => byte_we,
|
data_write => data_write,
|
data_write => data_write,
|
data_read => data_read,
|
data_read => data_read,
|
pause_in => mem_pause_in,
|
pause_in => eth_pause_in,
|
|
|
mem_address => mem_address, --from CPU
|
mem_address => cpu_address(31 downto 2), --from CPU
|
mem_byte_we => mem_byte_we,
|
mem_byte_we => cpu_byte_we,
|
data_w => data_w,
|
data_w => cpu_data_w,
|
pause_out => eth_pause,
|
pause_out => eth_pause,
|
|
|
E_RX_CLK => gpioA_in(20),
|
E_RX_CLK => gpioA_in(20),
|
E_RX_DV => gpioA_in(19),
|
E_RX_DV => gpioA_in(19),
|
E_RXD => gpioA_in(18 downto 15),
|
E_RXD => gpioA_in(18 downto 15),
|
| Line 238... |
Line 297... |
E_TXD => gpio0_out(27 downto 24));
|
E_TXD => gpio0_out(27 downto 24));
|
end generate;
|
end generate;
|
|
|
end; --architecture logic
|
end; --architecture logic
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