| Line 22... |
Line 22... |
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uart_read : in std_logic;
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uart_read : in std_logic;
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uart_write : out std_logic;
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uart_write : out std_logic;
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|
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mem_address_out : out std_logic_vector(31 downto 0);
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mem_address_out : out std_logic_vector(31 downto 0);
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mem_data : inout std_logic_vector(31 downto 0);
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mem_data : out std_logic_vector(31 downto 0);
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mem_byte_sel_out : out std_logic_vector(3 downto 0);
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mem_byte_sel_out : out std_logic_vector(3 downto 0);
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mem_write_out : out std_logic;
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mem_write_out : out std_logic;
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mem_pause_in : in std_logic);
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mem_pause_in : in std_logic);
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end; --entity plasma
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end; --entity plasma
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|
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architecture logic of plasma is
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architecture logic of plasma is
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signal clk : std_logic;
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signal mem_address : std_logic_vector(31 downto 0);
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signal mem_address : std_logic_vector(31 downto 0);
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signal mem_data_r : std_logic_vector(31 downto 0);
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signal mem_data_w : std_logic_vector(31 downto 0);
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signal mem_byte_sel : std_logic_vector(3 downto 0);
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signal mem_byte_sel : std_logic_vector(3 downto 0);
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signal mem_write : std_logic;
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signal mem_write : std_logic;
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signal mem_pause : std_logic;
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signal mem_pause : std_logic;
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signal mem_pause_uart : std_logic;
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signal mem_pause_uart : std_logic;
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signal uart_sel : std_logic;
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signal uart_sel : std_logic;
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begin --architecture
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begin --architecture
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clk_control1:
|
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if log_file = "UNUSED" generate
|
|
--convert 33MHz clock to 16.5MHz clock
|
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clk_div: process(clk_in, reset_in, clk)
|
|
begin
|
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if rising_edge(clk_in) then
|
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if reset_in = '1' then
|
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clk <= '0';
|
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else
|
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clk <= not clk;
|
|
end if;
|
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end if;
|
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end process; --clk_div
|
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end generate; --clk_control1
|
|
|
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clk_control2:
|
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if log_file /= "UNUSED" generate
|
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clk <= clk_in;
|
|
end generate; --clk_control2
|
|
|
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mem_pause <= mem_pause_in or mem_pause_uart;
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mem_pause <= mem_pause_in or mem_pause_uart;
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uart_sel <= '1' when mem_address(12 downto 0) = ONES(12 downto 0) and mem_byte_sel /= "0000" else
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uart_sel <= '1' when mem_address(12 downto 0) = ONES(12 downto 0) and mem_byte_sel /= "0000" else
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'0';
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'0';
|
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mem_data <= mem_data_r;
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|
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u1_cpu: mlite_cpu
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u1_cpu: mlite_cpu
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generic map (memory_type => memory_type)
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generic map (memory_type => memory_type)
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PORT MAP (
|
PORT MAP (
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clk => clk_in,
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clk => clk_in,
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reset_in => reset_in,
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reset_in => reset_in,
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intr_in => intr_in,
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intr_in => intr_in,
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|
|
mem_address => mem_address,
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mem_address => mem_address,
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mem_data_w => mem_data,
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mem_data_w => mem_data_w,
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mem_data_r => mem_data,
|
mem_data_r => mem_data_r,
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mem_byte_sel => mem_byte_sel,
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mem_byte_sel => mem_byte_sel,
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mem_write => mem_write,
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mem_write => mem_write,
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mem_pause => mem_pause);
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mem_pause => mem_pause);
|
|
|
u2_ram: ram
|
u2_ram: ram
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| Line 82... |
Line 64... |
PORT MAP (
|
PORT MAP (
|
clk => clk_in,
|
clk => clk_in,
|
mem_byte_sel => mem_byte_sel,
|
mem_byte_sel => mem_byte_sel,
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mem_write => mem_write,
|
mem_write => mem_write,
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mem_address => mem_address,
|
mem_address => mem_address,
|
mem_data => mem_data);
|
mem_data_w => mem_data_w,
|
|
mem_data_r => mem_data_r);
|
|
|
u3_uart: uart
|
u3_uart: uart
|
generic map (log_file => log_file)
|
generic map (log_file => log_file)
|
port map(
|
port map(
|
clk => clk_in,
|
clk => clk_in,
|
reset => reset_in,
|
reset => reset_in,
|
uart_sel => uart_sel,
|
uart_sel => uart_sel,
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data => mem_data(7 downto 0),
|
data => mem_data_w(7 downto 0),
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uart_write => uart_write,
|
uart_write => uart_write,
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uart_read => uart_read,
|
uart_read => uart_read,
|
pause => mem_pause_uart);
|
pause => mem_pause_uart);
|
|
|
mem_address_out <= mem_address;
|
mem_address_out <= mem_address;
|
