| Line 80... |
Line 80... |
architecture logic of plasma_3e is
|
architecture logic of plasma_3e is
|
|
|
component plasma
|
component plasma
|
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
|
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
|
log_file : string := "UNUSED";
|
log_file : string := "UNUSED";
|
ethernet : std_logic := '0');
|
ethernet : std_logic := '0';
|
|
use_cache : std_logic := '0');
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
uart_write : out std_logic;
|
uart_write : out std_logic;
|
uart_read : in std_logic;
|
uart_read : in std_logic;
|
|
|
address : out std_logic_vector(31 downto 2);
|
address : out std_logic_vector(31 downto 2);
|
byte_we : out std_logic_vector(3 downto 0);
|
byte_we : out std_logic_vector(3 downto 0);
|
data_write : out std_logic_vector(31 downto 0);
|
data_write : out std_logic_vector(31 downto 0);
|
data_read : in std_logic_vector(31 downto 0);
|
data_read : in std_logic_vector(31 downto 0);
|
mem_pause_in : in std_logic;
|
mem_pause_in : in std_logic;
|
|
no_ddr_start : out std_logic;
|
|
no_ddr_stop : out std_logic;
|
|
|
gpio0_out : out std_logic_vector(31 downto 0);
|
gpio0_out : out std_logic_vector(31 downto 0);
|
gpioA_in : in std_logic_vector(31 downto 0));
|
gpioA_in : in std_logic_vector(31 downto 0));
|
end component; --plasma
|
end component; --plasma
|
|
|
| Line 106... |
Line 109... |
address : in std_logic_vector(25 downto 2);
|
address : in std_logic_vector(25 downto 2);
|
byte_we : in std_logic_vector(3 downto 0);
|
byte_we : in std_logic_vector(3 downto 0);
|
data_w : in std_logic_vector(31 downto 0);
|
data_w : in std_logic_vector(31 downto 0);
|
data_r : out std_logic_vector(31 downto 0);
|
data_r : out std_logic_vector(31 downto 0);
|
active : in std_logic;
|
active : in std_logic;
|
|
no_start : in std_logic;
|
|
no_stop : in std_logic;
|
pause : out std_logic;
|
pause : out std_logic;
|
|
|
SD_CK_P : out std_logic; --clock_positive
|
SD_CK_P : out std_logic; --clock_positive
|
SD_CK_N : out std_logic; --clock_negative
|
SD_CK_N : out std_logic; --clock_negative
|
SD_CKE : out std_logic; --clock_enable
|
SD_CKE : out std_logic; --clock_enable
|
| Line 135... |
Line 140... |
signal data_r_ddr : std_logic_vector(31 downto 0);
|
signal data_r_ddr : std_logic_vector(31 downto 0);
|
signal byte_we : std_logic_vector(3 downto 0);
|
signal byte_we : std_logic_vector(3 downto 0);
|
signal write_enable : std_logic;
|
signal write_enable : std_logic;
|
signal pause_ddr : std_logic;
|
signal pause_ddr : std_logic;
|
signal pause : std_logic;
|
signal pause : std_logic;
|
|
signal no_ddr_start : std_logic;
|
|
signal no_ddr_stop : std_logic;
|
signal ddr_active : std_logic;
|
signal ddr_active : std_logic;
|
signal flash_active : std_logic;
|
signal flash_active : std_logic;
|
signal flash_cnt : std_logic_vector(1 downto 0);
|
signal flash_cnt : std_logic_vector(1 downto 0);
|
signal flash_we : std_logic;
|
signal flash_we : std_logic;
|
signal reset : std_logic;
|
signal reset : std_logic;
|
| Line 177... |
Line 184... |
write_enable <= '1' when byte_we /= "0000" else '0';
|
write_enable <= '1' when byte_we /= "0000" else '0';
|
|
|
u1_plama: plasma
|
u1_plama: plasma
|
generic map (memory_type => "XILINX_16X",
|
generic map (memory_type => "XILINX_16X",
|
log_file => "UNUSED",
|
log_file => "UNUSED",
|
ethernet => '1')
|
ethernet => '1',
|
|
use_cache => '1')
|
--generic map (memory_type => "DUAL_PORT_",
|
--generic map (memory_type => "DUAL_PORT_",
|
-- log_file => "output2.txt",
|
-- log_file => "output2.txt",
|
-- ethernet => '1')
|
-- ethernet => '1')
|
PORT MAP (
|
PORT MAP (
|
clk => clk_reg,
|
clk => clk_reg,
|
| Line 192... |
Line 200... |
address => address,
|
address => address,
|
byte_we => byte_we,
|
byte_we => byte_we,
|
data_write => data_write,
|
data_write => data_write,
|
data_read => data_read,
|
data_read => data_read,
|
mem_pause_in => pause,
|
mem_pause_in => pause,
|
|
no_ddr_start => no_ddr_start,
|
|
no_ddr_stop => no_ddr_stop,
|
|
|
gpio0_out => gpio0_out,
|
gpio0_out => gpio0_out,
|
gpioA_in => gpio0_in);
|
gpioA_in => gpio0_in);
|
|
|
u2_ddr: ddr_ctrl
|
u2_ddr: ddr_ctrl
|
| Line 207... |
Line 217... |
address => address(25 downto 2),
|
address => address(25 downto 2),
|
byte_we => byte_we,
|
byte_we => byte_we,
|
data_w => data_write,
|
data_w => data_write,
|
data_r => data_r_ddr,
|
data_r => data_r_ddr,
|
active => ddr_active,
|
active => ddr_active,
|
|
no_start => no_ddr_start,
|
|
no_stop => no_ddr_stop,
|
pause => pause_ddr,
|
pause => pause_ddr,
|
|
|
SD_CK_P => SD_CK_P, --clock_positive
|
SD_CK_P => SD_CK_P, --clock_positive
|
SD_CK_N => SD_CK_N, --clock_negative
|
SD_CK_N => SD_CK_N, --clock_negative
|
SD_CKE => SD_CKE, --clock_enable
|
SD_CKE => SD_CKE, --clock_enable
|
| Line 259... |
Line 271... |
|
|
SF_CE0 <= not flash_active;
|
SF_CE0 <= not flash_active;
|
SF_OE <= write_enable or not flash_active;
|
SF_OE <= write_enable or not flash_active;
|
SF_WE <= flash_we;
|
SF_WE <= flash_we;
|
SF_BYTE <= '1'; --16-bit access
|
SF_BYTE <= '1'; --16-bit access
|
SF_A <= address(25 downto 2) & '0';
|
SF_A <= address(25 downto 2) & '0' when flash_active = '1' else
|
|
"0000000000000000000000000";
|
SF_D <= data_write(15 downto 1) when
|
SF_D <= data_write(15 downto 1) when
|
flash_active = '1' and write_enable = '1'
|
flash_active = '1' and write_enable = '1'
|
else "ZZZZZZZZZZZZZZZ";
|
else "ZZZZZZZZZZZZZZZ";
|
SPI_MISO <= data_write(0) when
|
SPI_MISO <= data_write(0) when
|
flash_active = '1' and write_enable = '1'
|
flash_active = '1' and write_enable = '1'
|
