| Line 46... |
Line 46... |
reset : in std_logic;
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reset : in std_logic;
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uart_write : out std_logic;
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uart_write : out std_logic;
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uart_read : in std_logic;
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uart_read : in std_logic;
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|
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address : out std_logic_vector(31 downto 2);
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address : out std_logic_vector(31 downto 2);
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byte_we : out std_logic_vector(3 downto 0);
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data_write : out std_logic_vector(31 downto 0);
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data_write : out std_logic_vector(31 downto 0);
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data_read : in std_logic_vector(31 downto 0);
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data_read : in std_logic_vector(31 downto 0);
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write_byte_enable : out std_logic_vector(3 downto 0);
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mem_pause_in : in std_logic;
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mem_pause_in : in std_logic;
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|
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gpio0_out : out std_logic_vector(31 downto 0);
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gpio0_out : out std_logic_vector(31 downto 0);
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gpioA_in : in std_logic_vector(31 downto 0));
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gpioA_in : in std_logic_vector(31 downto 0));
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end component; --plasma
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end component; --plasma
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| Line 61... |
Line 61... |
signal we_n_next : std_logic;
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signal we_n_next : std_logic;
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signal we_n_reg : std_logic;
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signal we_n_reg : std_logic;
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signal mem_address : std_logic_vector(31 downto 2);
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signal mem_address : std_logic_vector(31 downto 2);
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signal data_write : std_logic_vector(31 downto 0);
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signal data_write : std_logic_vector(31 downto 0);
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signal data_reg : std_logic_vector(31 downto 0);
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signal data_reg : std_logic_vector(31 downto 0);
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signal write_byte_enable : std_logic_vector(3 downto 0);
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signal byte_we : std_logic_vector(3 downto 0);
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signal mem_pause_in : std_logic;
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signal mem_pause_in : std_logic;
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|
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begin --architecture
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begin --architecture
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--Divide 50 MHz clock by two
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--Divide 50 MHz clock by two
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clk_div: process(reset, clk_in, clk_reg, we_n_next)
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clk_div: process(reset, clk_in, clk_reg, we_n_next)
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| Line 89... |
Line 89... |
ram_address <= mem_address(31 downto 2);
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ram_address <= mem_address(31 downto 2);
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ram_we_n <= we_n_reg;
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ram_we_n <= we_n_reg;
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|
|
--For Xilinx Spartan-3 Starter Kit
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--For Xilinx Spartan-3 Starter Kit
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ram_control:
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ram_control:
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process(clk_reg, mem_address, write_byte_enable, data_write)
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process(clk_reg, mem_address, byte_we, data_write)
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begin
|
begin
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if mem_address(30 downto 28) = "001" then --RAM
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if mem_address(30 downto 28) = "001" then --RAM
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ram_ce1_n <= '0';
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ram_ce1_n <= '0';
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ram_ce2_n <= '0';
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ram_ce2_n <= '0';
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if write_byte_enable = "0000" then --read
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if byte_we = "0000" then --read
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ram_data <= (others => 'Z');
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ram_data <= (others => 'Z');
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ram_ub1_n <= '0';
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ram_ub1_n <= '0';
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ram_lb1_n <= '0';
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ram_lb1_n <= '0';
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ram_ub2_n <= '0';
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ram_ub2_n <= '0';
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ram_lb2_n <= '0';
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ram_lb2_n <= '0';
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| Line 108... |
Line 108... |
if clk_reg = '1' then
|
if clk_reg = '1' then
|
ram_data <= (others => 'Z');
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ram_data <= (others => 'Z');
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else
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else
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ram_data <= data_write;
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ram_data <= data_write;
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end if;
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end if;
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ram_ub1_n <= not write_byte_enable(3);
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ram_ub1_n <= not byte_we(3);
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ram_lb1_n <= not write_byte_enable(2);
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ram_lb1_n <= not byte_we(2);
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ram_ub2_n <= not write_byte_enable(1);
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ram_ub2_n <= not byte_we(1);
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ram_lb2_n <= not write_byte_enable(0);
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ram_lb2_n <= not byte_we(0);
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we_n_next <= '0';
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we_n_next <= '0';
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ram_oe_n <= '1';
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ram_oe_n <= '1';
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end if;
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end if;
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else
|
else
|
ram_data <= (others => 'Z');
|
ram_data <= (others => 'Z');
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| Line 138... |
Line 138... |
reset => reset,
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reset => reset,
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uart_write => uart_write,
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uart_write => uart_write,
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uart_read => uart_read,
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uart_read => uart_read,
|
|
|
address => mem_address,
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address => mem_address,
|
|
byte_we => byte_we,
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data_write => data_write,
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data_write => data_write,
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data_read => data_reg,
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data_read => data_reg,
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write_byte_enable => write_byte_enable,
|
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mem_pause_in => mem_pause_in,
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mem_pause_in => mem_pause_in,
|
|
|
gpio0_out => gpio0_out,
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gpio0_out => gpio0_out,
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gpioA_in => gpioA_in);
|
gpioA_in => gpioA_in);
|
|
|
