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[/] [mlite/] [trunk/] [vhdl/] [ram.vhd] - Diff between revs 139 and 260
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Rev 260 |
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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--Uncomment following two lines for Xilinx RAM16X1D
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library UNISIM; --Xilinx
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use UNISIM.vcomponents.all; --Xilinx
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entity ram is
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entity ram is
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generic(memory_type : string := "DEFAULT");
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generic(memory_type : string := "DEFAULT");
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port(clk : in std_logic;
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port(clk : in std_logic;
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enable : in std_logic;
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enable : in std_logic;
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