URL
https://opencores.org/ocsvn/mlite/mlite/trunk
[/] [mlite/] [trunk/] [vhdl/] [ram.vhd] - Diff between revs 139 and 260
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 139 |
Rev 260 |
| Line 17... |
Line 17... |
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_textio.all;
|
use ieee.std_logic_textio.all;
|
use std.textio.all;
|
use std.textio.all;
|
use work.mlite_pack.all;
|
use work.mlite_pack.all;
|
--Uncomment following two lines for Xilinx RAM16X1D
|
|
library UNISIM; --Xilinx
|
|
use UNISIM.vcomponents.all; --Xilinx
|
|
|
|
entity ram is
|
entity ram is
|
generic(memory_type : string := "DEFAULT");
|
generic(memory_type : string := "DEFAULT");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
enable : in std_logic;
|
enable : in std_logic;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
