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[/] [mlite/] [trunk/] [vhdl/] [ram.vhd] - Diff between revs 335 and 344

Rev 335	Rev 344
Line 34...	Line 34...
`constant ADDRESS_WIDTH : natural := 13;`	`constant ADDRESS_WIDTH : natural := 13;`
`begin`	`begin`

`generic_ram:`	`generic_ram:`
`if memory_type /= "ALTERA_LPM" generate`	`if memory_type /= "ALTERA_LPM" generate`
	`begin`
`--Simulate a synchronous RAM`	`--Simulate a synchronous RAM`
`ram_proc: process(clk, enable, write_byte_enable,`	`ram_proc: process(clk, enable, write_byte_enable,`
`address, data_write) --mem_write, mem_sel`	`address, data_write) --mem_write, mem_sel`
`variable mem_size : natural := 2 ** ADDRESS_WIDTH;`	`variable mem_size : natural := 2 ** ADDRESS_WIDTH;`
`variable data : std_logic_vector(31 downto 0);`	`variable data : std_logic_vector(31 downto 0);`
Line 91...	Line 92...


`altera_ram:`	`altera_ram:`
`if memory_type = "ALTERA_LPM" generate`	`if memory_type = "ALTERA_LPM" generate`
`signal byte_we : std_logic_vector(3 downto 0);`	`signal byte_we : std_logic_vector(3 downto 0);`
	`begin`
`byte_we <= write_byte_enable when enable = '1' else "0000";`	`byte_we <= write_byte_enable when enable = '1' else "0000";`
`lpm_ram_io_component0 : lpm_ram_dq`	`lpm_ram_io_component0 : lpm_ram_dq`
`GENERIC MAP (`	`GENERIC MAP (`
`intended_device_family => "UNUSED",`	`intended_device_family => "UNUSED",`
`lpm_width => 8,`	`lpm_width => 8,`