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[/] [mlite/] [trunk/] [vhdl/] [ram.vhd] - Diff between revs 11 and 39
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Random Access Memory
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-- TITLE: Random Access Memory
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 4/21/01
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-- DATE CREATED: 4/21/01
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-- FILENAME: ram.vhd
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-- FILENAME: ram.vhd
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-- PROJECT: MIPS CPU core
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-- PROJECT: M-lite CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Implements the RAM, reads the executable from "code.txt",
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-- Implements the RAM, reads the executable from "code.txt",
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-- and saves a character to "output.txt" upon a write to 0xffff.
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-- and saves a character to "output.txt" upon a write to 0xffff.
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mips_pack.all;
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use work.mlite_pack.all;
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entity ram is
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entity ram is
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generic(load_file_name : string);
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generic(load_file_name : string);
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port(clk : in std_logic;
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port(clk : in std_logic;
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mem_byte_sel : in std_logic_vector(3 downto 0);
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mem_byte_sel : in std_logic_vector(3 downto 0);
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