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[/] [mlite/] [trunk/] [vhdl/] [ram.vhd] - Diff between revs 11 and 39

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Rev 11 Rev 39
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---------------------------------------------------------------------
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 4/21/01
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- FILENAME: ram.vhd
-- PROJECT: MIPS CPU core
-- PROJECT: M-lite CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- COPYRIGHT: Software placed into the public domain by the author.
--    Software 'as is' without warranty.  Author liable for nothing.
--    Software 'as is' without warranty.  Author liable for nothing.
-- DESCRIPTION:
-- DESCRIPTION:
--    Implements the RAM, reads the executable from "code.txt",
--    Implements the RAM, reads the executable from "code.txt",
--    and saves a character to "output.txt" upon a write to 0xffff.
--    and saves a character to "output.txt" upon a write to 0xffff.
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use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use std.textio.all;
 
 
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
use work.mips_pack.all;
use work.mlite_pack.all;
 
 
entity ram is
entity ram is
   generic(load_file_name : string);
   generic(load_file_name : string);
   port(clk          : in std_logic;
   port(clk          : in std_logic;
        mem_byte_sel : in std_logic_vector(3 downto 0);
        mem_byte_sel : in std_logic_vector(3 downto 0);

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