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[/] [mlite/] [trunk/] [vhdl/] [reg_bank.vhd] - Diff between revs 123 and 128
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Rev 128 |
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Line 42... |
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--controls access to dual-port memories
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--controls access to dual-port memories
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signal addr_a1, addr_a2, addr_b : std_logic_vector(4 downto 0);
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signal addr_a1, addr_a2, addr_b : std_logic_vector(4 downto 0);
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signal data_out1, data_out2 : std_logic_vector(31 downto 0);
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signal data_out1, data_out2 : std_logic_vector(31 downto 0);
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signal write_enable : std_logic;
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signal write_enable : std_logic;
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-- signal sig_false : std_logic := '0';
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-- signal sig_true : std_logic := '1';
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-- signal zero_sig : std_logic_vector(15 downto 0) := ZERO(15 downto 0);
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begin
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begin
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reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
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reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
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intr_enable_reg, data_out1, data_out2, reset_in, pause)
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intr_enable_reg, data_out1, data_out2, reset_in, pause)
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