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[/] [mlite/] [trunk/] [vhdl/] [reg_bank.vhd] - Diff between revs 128 and 132
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| Rev 128 |
Rev 132 |
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Line 14... |
use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity reg_bank is
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entity reg_bank is
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generic(memory_type : string := "GENERIC");
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generic(memory_type : string := "DEFAULT");
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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pause : in std_logic;
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pause : in std_logic;
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rs_index : in std_logic_vector(5 downto 0);
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rs_index : in std_logic_vector(5 downto 0);
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rt_index : in std_logic_vector(5 downto 0);
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rt_index : in std_logic_vector(5 downto 0);
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Line 105... |
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-- Option #1
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-- Option #1
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-- One tri-port RAM, two read-ports, one write-port
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-- One tri-port RAM, two read-ports, one write-port
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-- 32 registers 32-bits wide
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-- 32 registers 32-bits wide
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tri_port_mem:
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tri_port_mem:
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if memory_type = "GENERIC" generate
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if memory_type = "DEFAULT" generate
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ram_proc: process(clk, addr_a1, addr_a2, addr_b, reg_dest_new,
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ram_proc: process(clk, addr_a1, addr_a2, addr_b, reg_dest_new,
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write_enable)
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write_enable)
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variable tri_port_ram : ram_type;
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variable tri_port_ram : ram_type;
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begin
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begin
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data_out1 <= tri_port_ram(conv_integer(addr_a1));
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data_out1 <= tri_port_ram(conv_integer(addr_a1));
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