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Line 236... |
-- Option #4
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-- Option #4
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-- Altera LPM_RAM_DP
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-- Altera LPM_RAM_DP
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-- Xilinx users may need to comment out this section!!!
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-- Xilinx users may need to comment out this section!!!
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altera_mem:
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altera_mem:
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if memory_type = "ALTERA_LPM" generate
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if memory_type = "ALTERA_LPM" generate
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signal clk_delayed : std_logic;
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signal addr_reg : std_logic_vector(4 downto 0);
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signal data_reg : std_logic_vector(31 downto 0);
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signal q1 : std_logic_vector(31 downto 0);
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signal q2 : std_logic_vector(31 downto 0);
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begin
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-- Altera dual port RAMs must have the addresses registered (sampled
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-- at the rising edge). This is very unfortunate.
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-- Therefore, the dual port RAM read clock must delayed so that
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-- the read address signal can be sent from the mem_ctrl block.
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-- This solution also delays the how fast the registers are read so the
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-- maximum clock speed is cut in half (12.5 MHz instead of 25 MHz).
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clk_delayed <= not clk; --Could be delayed by 1/4 clock cycle instead
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dpram_bypass: process(clk, addr_write, reg_dest_new)
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begin
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if rising_edge(clk) and write_enable = '1' then
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addr_reg <= addr_write;
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data_reg <= reg_dest_new;
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end if;
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end process; --dpram_bypass
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-- Bypass dpram if reading what was just written (Altera limitation)
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data_out1 <= q1 when addr_read1 /= addr_reg else data_reg;
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data_out2 <= q2 when addr_read2 /= addr_reg else data_reg;
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lpm_ram_dp_component1 : lpm_ram_dp
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lpm_ram_dp_component1 : lpm_ram_dp
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GENERIC MAP (
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generic map (
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lpm_width => 32,
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LPM_WIDTH => 32,
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lpm_widthad => 5,
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LPM_WIDTHAD => 5,
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rden_used => "FALSE",
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--LPM_NUMWORDS => 0,
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intended_device_family => "UNUSED",
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LPM_INDATA => "REGISTERED",
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lpm_indata => "REGISTERED",
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LPM_OUTDATA => "UNREGISTERED",
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lpm_wraddress_control => "REGISTERED",
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LPM_RDADDRESS_CONTROL => "REGISTERED",
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lpm_rdaddress_control => "UNREGISTERED",
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LPM_WRADDRESS_CONTROL => "REGISTERED",
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lpm_outdata => "UNREGISTERED",
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LPM_FILE => "UNUSED",
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use_eab => "ON",
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LPM_TYPE => "LPM_RAM_DP",
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lpm_type => "LPM_RAM_DP"
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USE_EAB => "ON",
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)
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INTENDED_DEVICE_FAMILY => "UNUSED",
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PORT MAP (
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RDEN_USED => "FALSE",
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wren => write_enable,
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LPM_HINT => "UNUSED")
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wrclock => clk,
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port map (
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data => reg_dest_new,
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RDCLOCK => clk_delayed,
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rdaddress => addr_read1,
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RDCLKEN => '1',
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wraddress => addr_write,
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RDADDRESS => addr_read1,
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q => data_out1
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RDEN => '1',
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);
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DATA => reg_dest_new,
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WRADDRESS => addr_write,
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WREN => write_enable,
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WRCLOCK => clk,
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WRCLKEN => '1',
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Q => q1);
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lpm_ram_dp_component2 : lpm_ram_dp
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lpm_ram_dp_component2 : lpm_ram_dp
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GENERIC MAP (
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generic map (
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lpm_width => 32,
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LPM_WIDTH => 32,
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lpm_widthad => 5,
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LPM_WIDTHAD => 5,
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rden_used => "FALSE",
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--LPM_NUMWORDS => 0,
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intended_device_family => "UNUSED",
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LPM_INDATA => "REGISTERED",
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lpm_indata => "REGISTERED",
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LPM_OUTDATA => "UNREGISTERED",
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lpm_wraddress_control => "REGISTERED",
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LPM_RDADDRESS_CONTROL => "REGISTERED",
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lpm_rdaddress_control => "UNREGISTERED",
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LPM_WRADDRESS_CONTROL => "REGISTERED",
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lpm_outdata => "UNREGISTERED",
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LPM_FILE => "UNUSED",
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use_eab => "ON",
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LPM_TYPE => "LPM_RAM_DP",
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lpm_type => "LPM_RAM_DP"
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USE_EAB => "ON",
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)
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INTENDED_DEVICE_FAMILY => "UNUSED",
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PORT MAP (
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RDEN_USED => "FALSE",
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wren => write_enable,
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LPM_HINT => "UNUSED")
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wrclock => clk,
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port map (
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data => reg_dest_new,
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RDCLOCK => clk_delayed,
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rdaddress => addr_read2,
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RDCLKEN => '1',
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wraddress => addr_write,
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RDADDRESS => addr_read2,
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q => data_out2
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RDEN => '1',
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);
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DATA => reg_dest_new,
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WRADDRESS => addr_write,
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WREN => write_enable,
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WRCLOCK => clk,
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WRCLKEN => '1',
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Q => q2);
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end generate; --altera_mem
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end generate; --altera_mem
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end; --architecture ram_block
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end; --architecture ram_block
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No newline at end of file
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No newline at end of file
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