| Line 24... |
Line 24... |
reg_target_out : out std_logic_vector(31 downto 0);
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reg_target_out : out std_logic_vector(31 downto 0);
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reg_dest_new : in std_logic_vector(31 downto 0);
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reg_dest_new : in std_logic_vector(31 downto 0);
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intr_enable : out std_logic);
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intr_enable : out std_logic);
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end; --entity reg_bank
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end; --entity reg_bank
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- Change mips_cpu.vhd to use the ram_block architecture.
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-- Change mips_cpu.vhd to use the ram_block architecture.
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-- The ram_block architecture attempts to used TWO dual-port memories.
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-- The ram_block architecture attempts to use TWO dual-port memories.
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-- If the dual-port memory supports a write and two read ports then
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-- For a tri-port memory with one write and two read ports then
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-- change all references of ram_rt to ram_rs so only one dual-port
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-- remove dual_port_ram2 so only one tri-port memory will be created.
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-- memory will be created.
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-- According to the Xilinx answers database record #4075 this architecture
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-- According to the Xilinx answers database record #4075 this architecture
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-- may cause Synplify to infer a synchronous dual-port RAM using RAM16x1D.
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-- may cause Synplify to infer a synchronous dual-port RAM using RAM16x1D.
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-- For Altera use either a csdpram or lpm_ram_dq.
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-- For Altera use either a csdpram or lpm_ram_dq.
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-- I need feedback on this section!
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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architecture ram_block of reg_bank is
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architecture ram_block of reg_bank is
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type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
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signal ram_rs : ram_type;
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signal ram_rt : ram_type;
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signal reg_status : std_logic;
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signal reg_status : std_logic;
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type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
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signal dual_port_ram1 : ram_type;
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signal dual_port_ram2 : ram_type;
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attribute block_ram : boolean;
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--controls access to dual-port memories
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attribute block_ram of ram_rs : signal is TRUE;
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signal addr_a1, addr_a2, addr_b : std_logic_vector(4 downto 0);
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attribute block_ram of ram_rt : signal is TRUE;
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signal data_out1, data_out2 : std_logic_vector(31 downto 0);
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signal write_enable : std_logic;
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begin
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begin
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reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
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reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
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reg_status)
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reg_status, data_out1, data_out2)
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variable rs, rt, rd : natural;
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begin
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begin
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--setup for first dual-port memory
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rs := conv_integer(rs_index(4 downto 0));
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if rs_index = "101110" then --reg_epc CP0 14
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addr_a1 <= "00000";
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else
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addr_a1 <= rs_index(4 downto 0);
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end if;
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case rs_index is
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case rs_index is
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when "000000" => reg_source_out <= ZERO;
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when "000000" => reg_source_out <= ZERO;
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when "101100" => reg_source_out <= ZERO(31 downto 1) & reg_status;
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when "101100" => reg_source_out <= ZERO(31 downto 1) & reg_status;
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when "111111" => reg_source_out <= ZERO(31 downto 8) & "00110000"; --intr vector
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when "111111" => reg_source_out <= ZERO(31 downto 8) & "00110000"; --intr vector
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when others =>
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when others => reg_source_out <= data_out1;
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if rs_index = "101110" then --reg_epc CP0 14
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rs := 0;
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end if;
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reg_source_out <= ram_rs(rs);
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end case;
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end case;
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rt := conv_integer(rt_index(4 downto 0));
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--setup for second dual-port memory
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addr_a2 <= rt_index(4 downto 0);
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case rt_index is
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case rt_index is
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when "000000" => reg_target_out <= ZERO;
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when "000000" => reg_target_out <= ZERO;
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when others => reg_target_out <= ram_rt(rt);
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when others => reg_target_out <= data_out2;
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end case;
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end case;
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if rising_edge(clk) then
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--setup second port (write port) for both dual-port memories
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rd := conv_integer(rd_index(4 downto 0));
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if rd_index /= "000000" and rd_index /= "101100" then
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case rd_index is
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write_enable <= '1';
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when "000000" =>
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else
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when "101100" => reg_status <= reg_dest_new(0);
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write_enable <= '0';
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when others =>
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end if;
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if rd_index = "101110" then --reg_epc CP0 14
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if rd_index = "101110" then --reg_epc CP0 14
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rd := 0;
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addr_b <= "00000";
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else
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addr_b <= rd_index(4 downto 0);
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end if;
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|
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if rising_edge(clk) then
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if rd_index = "101100" then
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reg_status <= reg_dest_new(0);
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elsif rd_index = "101110" then --reg_epc CP0 14
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reg_status <= '0'; --disable interrupts
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reg_status <= '0'; --disable interrupts
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end if;
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end if;
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ram_rs(rd) <= reg_dest_new;
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ram_rt(rd) <= reg_dest_new;
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end case;
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end if;
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end if;
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intr_enable <= reg_status;
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intr_enable <= reg_status;
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end process;
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ram_proc: process(clk, addr_a1, addr_a2, addr_b, reg_dest_new,
|
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write_enable, dual_port_ram1, dual_port_ram2)
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begin
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-- Simulate two dual-port RAMs
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data_out1 <= dual_port_ram1(conv_integer(addr_a1));
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data_out2 <= dual_port_ram2(conv_integer(addr_a2));
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if rising_edge(clk) then
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if write_enable = '1' then
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dual_port_ram1(conv_integer(addr_b)) <= reg_dest_new;
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dual_port_ram2(conv_integer(addr_b)) <= reg_dest_new;
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end if;
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end if;
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-- Simulate one tri-port RAM
|
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-- Remember to comment out dual_port_ram2
|
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-- data_out1 <= dual_port_ram1(conv_integer(addr_a1));
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-- data_out2 <= dual_port_ram1(conv_integer(addr_a2));
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-- if rising_edge(clk) then
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-- if write_enable = '1' then
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-- dual_port_ram1(conv_integer(addr_b)) <= reg_dest_new;
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-- end if;
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-- end if;
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|
|
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-- Generic Two-Port Synchronous RAM
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-- generic_tpram can be obtained from:
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-- http://www.opencores.org/cvsweb.shtml/generic_memories/
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-- Supports ASICs (Artisan, Avant, and Virage) and Xilinx FPGA
|
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-- Remember to comment out dual_port_ram1 and dual_port_ram2
|
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-- bank1 : generic_tpram port map (
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-- clk_a => clk,
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-- rst_a => '0',
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-- ce_a => '1',
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-- we_a => '0',
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-- oe_a => '1',
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-- addr_a => addr_a1,
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-- di_a => ZERO,
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-- do_a => data_out1,
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--
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-- clk_b => clk,
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-- rst_b => '0',
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-- ce_b => '1',
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-- we_b => write_enable,
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-- oe_b => '0',
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-- addr_b => addr_b,
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-- di_a => reg_dest_new);
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--
|
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-- bank2 : generic_tpram port map (
|
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-- clk_a => clk,
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-- rst_a => '0',
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-- ce_a => '1',
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-- we_a => '0',
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-- oe_a => '1',
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-- addr_a => addr_a2,
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-- di_a => ZERO,
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-- do_a => data_out2,
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--
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-- clk_b => clk,
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-- rst_b => '0',
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-- ce_b => '1',
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-- we_b => write_enable,
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-- oe_b => '0',
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-- addr_b => addr_b,
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-- di_a => reg_dest_new);
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|
|
|
|
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-- Xilinx mode using four 16x16 banks
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-- Remember to comment out dual_port_ram1 and dual_port_ram2
|
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-- bank1_high: ramb4_s16_s16 port map (
|
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-- clka => clk,
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-- rsta => sig_false,
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-- addra => addr_a1,
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-- dia => ZERO(31 downto 16),
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-- ena => sig_true,
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-- wea => sig_false,
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-- doa => data_out1(31 downto 16),
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--
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-- clkb => clk,
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-- rstb => sig_false,
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-- addrb => addr_b,
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-- dib => reg_dest_new(31 downto 16),
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-- enb => sig_true,
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-- web => write_enable);
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--
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-- bank1_low: ramb4_s16_s16 port map (
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-- clka => clk,
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-- rsta => sig_false,
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-- addra => addr_a1,
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-- dia => ZERO(15 downto 0),
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-- ena => sig_true,
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-- wea => sig_false,
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-- doa => data_out1(15 downto 0),
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--
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-- clkb => clk,
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-- rstb => sig_false,
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-- addrb => addr_b,
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-- dib => reg_dest_new(15 downto 0),
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-- enb => sig_true,
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-- web => write_enable);
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--
|
|
-- bank2_high: ramb4_s16_s16 port map (
|
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-- clka => clk,
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-- rsta => sig_false,
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-- addra => addr_a2,
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-- dia => ZERO(31 downto 16),
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-- ena => sig_true,
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-- wea => sig_false,
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-- doa => data_out2(31 downto 16),
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--
|
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-- clkb => clk,
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-- rstb => sig_false,
|
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-- addrb => addr_b,
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-- dib => reg_dest_new(31 downto 16),
|
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-- enb => sig_true,
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|
-- web => write_enable);
|
|
--
|
|
-- bank2_low: ramb4_s16_s16 port map (
|
|
-- clka => clk,
|
|
-- rsta => sig_false,
|
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-- addra => addr_a2,
|
|
-- dia => ZERO(15 downto 0),
|
|
-- ena => sig_true,
|
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-- wea => sig_false,
|
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-- doa => data_out2(15 downto 0),
|
|
--
|
|
-- clkb => clk,
|
|
-- rstb => sig_false,
|
|
-- addrb => addr_b,
|
|
-- dib => reg_dest_new(15 downto 0),
|
|
-- enb => sig_true,
|
|
-- web => write_enable);
|
|
|
end process;
|
end process;
|
|
|
end; --architecture ram_block
|
end; --architecture ram_block
|
|
|
