OpenCores
URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] [shifter.vhd] - Diff between revs 118 and 128

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 118 Rev 128
Line 30... Line 30...
signal shift1L, shift2L, shift4L, shift8L, shift16L : std_logic_vector(31 downto 0);
signal shift1L, shift2L, shift4L, shift8L, shift16L : std_logic_vector(31 downto 0);
signal shift1R, shift2R, shift4R, shift8R, shift16R : std_logic_vector(31 downto 0);
signal shift1R, shift2R, shift4R, shift8R, shift16R : std_logic_vector(31 downto 0);
signal fills : std_logic_vector(31 downto 16);
signal fills : std_logic_vector(31 downto 16);
 
 
begin
begin
   fills <= "1111111111111111" when shift_func = shift_right_signed and value(31) = '1' else
   fills <= "1111111111111111" when shift_func = SHIFT_RIGHT_SIGNED and value(31) = '1' else
            "0000000000000000";
            "0000000000000000";
   shift1L <= value(30 downto 0) & '0' when shift_amount(0) = '1' else value;
   shift1L <= value(30 downto 0) & '0' when shift_amount(0) = '1' else value;
   shift2L <= shift1L(29 downto 0) & "00" when shift_amount(1) = '1' else shift1L;
   shift2L <= shift1L(29 downto 0) & "00" when shift_amount(1) = '1' else shift1L;
   shift4L <= shift2L(27 downto 0) & "0000" when shift_amount(2) = '1' else shift2L;
   shift4L <= shift2L(27 downto 0) & "0000" when shift_amount(2) = '1' else shift2L;
   shift8L <= shift4L(23 downto 0) & "00000000" when shift_amount(3) = '1' else shift4L;
   shift8L <= shift4L(23 downto 0) & "00000000" when shift_amount(3) = '1' else shift4L;
Line 48... Line 48...
 
 
-- synthesis translate_off
-- synthesis translate_off
GENERIC_SHIFTER: if shifter_type = "GENERIC" generate
GENERIC_SHIFTER: if shifter_type = "GENERIC" generate
-- synthesis translate_on
-- synthesis translate_on
 
 
   c_shift <= shift16L when shift_func = shift_left_unsigned else
   c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else
              shift16R when shift_func = shift_right_unsigned or shift_func = shift_right_signed else
              shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or shift_func = SHIFT_RIGHT_SIGNED else
              ZERO;
              ZERO;
 
 
-- synthesis translate_off
-- synthesis translate_off
end generate;
end generate;
-- synthesis translate_on
-- synthesis translate_on
 
 
-- synopsys synthesis_off
-- synopsys synthesis_off
 
 
AREA_OPTIMIZED_SHIFTER: if shifter_type = "AREA_OPTIMIZED" generate
AREA_OPTIMIZED_SHIFTER: if shifter_type = "AREA_OPTIMIZED" generate
 
 
   c_shift <= shift16L when shift_func = shift_left_unsigned else (others => 'Z');
   c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else (others => 'Z');
   c_shift <= shift16R when shift_func = shift_right_unsigned or
   c_shift <= shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
                            shift_func = shift_right_signed else (others => 'Z');
                            shift_func = SHIFT_RIGHT_SIGNED else (others => 'Z');
   c_shift <= ZERO     when shift_func = shift_nothing else (others => 'Z');
   c_shift <= ZERO     when shift_func = SHIFT_NOTHING else (others => 'Z');
 
 
end generate;
end generate;
 
 
-- synopsys synthesis_on
-- synopsys synthesis_on
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.