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   signal uart_read   : std_logic;

   signal uart_read   : std_logic;

   signal uart_write  : std_logic;

   signal uart_write  : std_logic;

begin  --architecture

begin  --architecture

   clk <= not clk after 50 ns;

   clk <= not clk after 50 ns;

   reset <= '0' after 500 ns;

   reset <= '0' after 500 ns;

   --Uncomment the line below to test interrupts

   --Uncomment the line below to test interrupts

--   interrupt <= '1' after 20 us when interrupt = '0' else '0' after 400 ns;

--   interrupt <= '1' after 20 us when interrupt = '0' else '0' after 400 ns;

   --Uncomment the line below to test mem_pause

   --Uncomment the line below to test mem_pause

--   mem_pause <= '1' after 100 ns when mem_pause = '0' else '0' after 100 ns;

--   mem_pause <= '1' after 100 ns when mem_pause = '0' else '0' after 100 ns;