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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Test Bench
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-- TITLE: Test Bench
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 4/21/01
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-- DATE CREATED: 4/21/01
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-- FILENAME: tbench.vhd
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-- FILENAME: tbench.vhd
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-- PROJECT: MIPS CPU core
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-- PROJECT: M-lite CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- This entity provides a test bench for testing the MIPS CPU core.
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-- This entity provides a test bench for testing the M-lite CPU core.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mips_pack.all;
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use work.mlite_pack.all;
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entity tbench is
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entity tbench is
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end; --entity tbench
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end; --entity tbench
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architecture logic of tbench is
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architecture logic of tbench is
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component mips_cpu
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component mlite_cpu
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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intr_in : in std_logic;
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intr_in : in std_logic;
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mem_address : out std_logic_vector(31 downto 0);
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mem_address : out std_logic_vector(31 downto 0);
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clk <= not clk after 50 ns;
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clk <= not clk after 50 ns;
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reset <= '0' after 320 ns;
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reset <= '0' after 320 ns;
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mem_pause <= '0';
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mem_pause <= '0';
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--Uncomment the line below to test interrupts
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--Uncomment the line below to test interrupts
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-- interrupt <= '1' after 10 us when interrupt = '0' else '0' after 600 ns;
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-- interrupt <= '1' after 20 us when interrupt = '0' else '0' after 400 ns;
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u1: mips_cpu PORT MAP (
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u1: mlite_cpu PORT MAP (
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clk => clk,
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clk => clk,
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reset_in => reset,
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reset_in => reset,
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intr_in => interrupt,
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intr_in => interrupt,
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mem_address => mem_address,
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mem_address => mem_address,
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