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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity tbench is
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entity tbench is
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port(write_pin : out std_logic;
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read_pin : in std_logic);
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end; --entity tbench
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end; --entity tbench
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architecture logic of tbench is
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architecture logic of tbench is
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constant memory_type : string := "GENERIC";
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component mlite_cpu
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-- constant memory_type : string := "ALTERA";
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port(clk : in std_logic;
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-- constant memory_type : string := "XILINX";
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reset_in : in std_logic;
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intr_in : in std_logic;
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mem_address : out std_logic_vector(31 downto 0);
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mem_data_w : out std_logic_vector(31 downto 0);
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mem_data_r : in std_logic_vector(31 downto 0);
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mem_byte_sel: out std_logic_vector(3 downto 0);
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mem_write : out std_logic;
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mem_pause : in std_logic);
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end component;
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component ram
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generic(load_file_name : string);
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port(clk : in std_logic;
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mem_byte_sel : in std_logic_vector(3 downto 0);
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mem_write : in std_logic;
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mem_address : in std_logic_vector;
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mem_data_w : in std_logic_vector(31 downto 0);
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mem_data_r : out std_logic_vector(31 downto 0));
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end component;
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signal clk : std_logic := '1';
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signal clk : std_logic := '1';
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signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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signal interrupt : std_logic := '0';
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signal interrupt : std_logic := '0';
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signal mem_write : std_logic;
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signal mem_write : std_logic;
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signal mem_read : std_logic;
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signal mem_address : std_logic_vector(31 downto 0);
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signal mem_address : std_logic_vector(31 downto 0);
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signal mem_data_w : std_logic_vector(31 downto 0);
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signal mem_data : std_logic_vector(31 downto 0);
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signal mem_data_r : std_logic_vector(31 downto 0);
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signal mem_pause : std_logic := '0';
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signal mem_pause : std_logic;
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signal mem_byte_sel: std_logic_vector(3 downto 0);
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signal mem_byte_sel: std_logic_vector(3 downto 0);
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signal uart_sel : std_logic;
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begin --architecture
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begin --architecture
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clk <= not clk after 50 ns;
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clk <= not clk after 50 ns;
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reset <= '0' after 320 ns;
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reset <= '0' after 320 ns;
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mem_pause <= '0';
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-- mem_pause <= '0';
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mem_read <= not mem_write;
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uart_sel <= '1' when mem_address(12 downto 0) = ONES(12 downto 0) and mem_byte_sel /= "0000" else
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'0';
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--Uncomment the line below to test interrupts
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--Uncomment the line below to test interrupts
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-- interrupt <= '1' after 20 us when interrupt = '0' else '0' after 400 ns;
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-- interrupt <= '1' after 20 us when interrupt = '0' else '0' after 400 ns;
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u1: mlite_cpu PORT MAP (
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u1: mlite_cpu
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generic map (memory_type => memory_type)
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PORT MAP (
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clk => clk,
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clk => clk,
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reset_in => reset,
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reset_in => reset,
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intr_in => interrupt,
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intr_in => interrupt,
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mem_address => mem_address,
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mem_address => mem_address,
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mem_data_w => mem_data_w,
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mem_data_w => mem_data,
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mem_data_r => mem_data_r,
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mem_data_r => mem_data,
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mem_byte_sel => mem_byte_sel,
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mem_byte_sel => mem_byte_sel,
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mem_write => mem_write,
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mem_write => mem_write,
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mem_pause => mem_pause);
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mem_pause => mem_pause);
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u2: ram generic map ("code.txt")
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generic_ram:
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if memory_type /= "ALTERA" generate
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u2: ram
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generic map ("code.txt")
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PORT MAP (
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PORT MAP (
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clk => clk,
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clk => clk,
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mem_byte_sel => mem_byte_sel,
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mem_byte_sel => mem_byte_sel,
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mem_write => mem_write,
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mem_write => mem_write,
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mem_address => mem_address(15 downto 0),
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mem_address => mem_address(15 downto 0),
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mem_data_w => mem_data_w,
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mem_data_w => mem_data,
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mem_data_r => mem_data_r);
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mem_data_r => mem_data);
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end generate; --generic_ram
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altera_ram:
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if memory_type = "ALTERA" generate
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uart_component: uart
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generic map ("output.txt")
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port map(
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clk => clk,
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reset => reset,
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uart_sel => uart_sel,
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data => mem_data(7 downto 0),
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write_pin => write_pin,
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read_pin => read_pin,
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pause => mem_pause);
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lpm_ram_io_component0 : lpm_ram_io
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GENERIC MAP (
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intended_device_family => "UNUSED",
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lpm_width => 8,
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lpm_widthad => 11,
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lpm_indata => "REGISTERED",
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lpm_address_control => "UNREGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_file => "code0.hex",
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use_eab => "ON",
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lpm_type => "LPM_RAM_DQ")
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PORT MAP (
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outenab => mem_read,
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address => mem_address(12 downto 2),
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inclock => clk,
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we => mem_byte_sel(3),
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dio => mem_data(31 downto 24));
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lpm_ram_io_component1 : lpm_ram_io
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GENERIC MAP (
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intended_device_family => "UNUSED",
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lpm_width => 8,
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lpm_widthad => 11,
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lpm_indata => "REGISTERED",
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lpm_address_control => "UNREGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_file => "code1.hex",
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use_eab => "ON",
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lpm_type => "LPM_RAM_DQ")
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PORT MAP (
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outenab => mem_read,
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address => mem_address(12 downto 2),
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inclock => clk,
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we => mem_byte_sel(2),
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dio => mem_data(23 downto 16));
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lpm_ram_io_component2 : lpm_ram_io
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GENERIC MAP (
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intended_device_family => "UNUSED",
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lpm_width => 8,
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lpm_widthad => 11,
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lpm_indata => "REGISTERED",
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lpm_address_control => "UNREGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_file => "code2.hex",
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use_eab => "ON",
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lpm_type => "LPM_RAM_DQ")
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PORT MAP (
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outenab => mem_read,
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address => mem_address(12 downto 2),
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inclock => clk,
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we => mem_byte_sel(1),
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dio => mem_data(15 downto 8));
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lpm_ram_io_component3 : lpm_ram_io
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GENERIC MAP (
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intended_device_family => "UNUSED",
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lpm_width => 8,
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lpm_widthad => 11,
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lpm_indata => "REGISTERED",
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lpm_address_control => "UNREGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_file => "code3.hex",
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use_eab => "ON",
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lpm_type => "LPM_RAM_DQ")
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PORT MAP (
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outenab => mem_read,
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address => mem_address(12 downto 2),
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inclock => clk,
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we => mem_byte_sel(0),
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dio => mem_data(7 downto 0));
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end generate; --altera_ram
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end; --architecture logic
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end; --architecture logic
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No newline at end of file
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No newline at end of file
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