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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mips_pack.all;
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use work.mips_pack.all;
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entity tbench is
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entity tbench is
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port(clk_out : out std_logic;
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port(clk_out : out std_logic);
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pc : out std_logic_vector(31 downto 0)
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);
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end; --entity tbench
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end; --entity tbench
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architecture logic of tbench is
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architecture logic of tbench is
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component mips_cpu
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component mips_cpu
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intr_in : in std_logic;
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intr_in : in std_logic;
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mem_address : out std_logic_vector(31 downto 0);
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mem_address : out std_logic_vector(31 downto 0);
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mem_data_w : out std_logic_vector(31 downto 0);
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mem_data_w : out std_logic_vector(31 downto 0);
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mem_data_r : in std_logic_vector(31 downto 0);
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mem_data_r : in std_logic_vector(31 downto 0);
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mem_sel : out std_logic_vector(3 downto 0);
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mem_byte_sel: out std_logic_vector(3 downto 0);
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mem_write : out std_logic;
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mem_write : out std_logic;
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mem_pause : in std_logic;
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mem_pause : in std_logic);
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t_pc : out std_logic_vector(31 downto 0);
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t_opcode : out std_logic_vector(31 downto 0);
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t_r_dest : out std_logic_vector(31 downto 0)
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);
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end component;
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end component;
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component ram
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component ram
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generic(load_file_name : string);
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generic(load_file_name : string);
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port(clk : in std_logic;
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port(clk : in std_logic;
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mem_address : in std_logic_vector;
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mem_address : in std_logic_vector;
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mem_data_w : in std_logic_vector(31 downto 0);
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mem_data_w : in std_logic_vector(31 downto 0);
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mem_data_r : out std_logic_vector(31 downto 0));
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mem_data_r : out std_logic_vector(31 downto 0));
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end component;
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end component;
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signal clk : std_logic := '0';
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signal clk : std_logic := '1';
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signal reset : std_logic := '1'; --, '0' after 100 ns;
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signal reset : std_logic := '1';
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signal interrupt : std_logic := '0';
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signal interrupt : std_logic := '0';
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signal mem_sel : std_logic_vector(3 downto 0);
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signal mem_write : std_logic;
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signal mem_write : std_logic;
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signal mem_address : std_logic_vector(31 downto 0);
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signal mem_address : std_logic_vector(31 downto 0);
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signal mem_data_w : std_logic_vector(31 downto 0);
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signal mem_data_w : std_logic_vector(31 downto 0);
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signal mem_data_r : std_logic_vector(31 downto 0);
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signal mem_data_r : std_logic_vector(31 downto 0);
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signal mem_pause : std_logic;
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signal mem_pause : std_logic;
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signal t_pc : std_logic_vector(31 downto 0);
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signal t_opcode : std_logic_vector(31 downto 0);
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signal t_r_dest : std_logic_vector(31 downto 0);
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signal mem_byte_sel: std_logic_vector(3 downto 0);
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signal mem_byte_sel: std_logic_vector(3 downto 0);
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begin --architecture
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begin --architecture
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clk <= not clk after 50 ns;
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clk <= not clk after 50 ns;
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reset <= '0' after 100 ns;
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reset <= '0' after 320 ns;
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mem_pause <= '0';
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mem_pause <= '0';
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--Uncomment the line below to test interrupts
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--Uncomment the line below to test interrupts
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-- interrupt <= '1' after 10000 ns when interrupt = '0' else '0' after 600 ns;
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-- interrupt <= '1' after 10 us when interrupt = '0' else '0' after 600 ns;
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u1: mips_cpu PORT MAP (
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u1: mips_cpu PORT MAP (
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clk => clk,
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clk => clk,
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reset_in => reset,
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reset_in => reset,
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intr_in => interrupt,
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intr_in => interrupt,
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mem_address => mem_address,
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mem_address => mem_address,
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mem_data_w => mem_data_w,
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mem_data_w => mem_data_w,
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mem_data_r => mem_data_r,
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mem_data_r => mem_data_r,
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mem_sel => mem_byte_sel,
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mem_byte_sel => mem_byte_sel,
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mem_write => mem_write,
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mem_write => mem_write,
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mem_pause => mem_pause,
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mem_pause => mem_pause);
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t_pc => t_pc,
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t_opcode => t_opcode,
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t_r_dest => t_r_dest);
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u2: ram generic map ("code.txt")
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u2: ram generic map ("code.txt")
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PORT MAP (
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PORT MAP (
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clk => clk,
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clk => clk,
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mem_byte_sel => mem_byte_sel,
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mem_byte_sel => mem_byte_sel,
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mem_address => mem_address(15 downto 0),
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mem_address => mem_address(15 downto 0),
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mem_data_w => mem_data_w,
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mem_data_w => mem_data_w,
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mem_data_r => mem_data_r);
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mem_data_r => mem_data_r);
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clk_out <= clk;
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clk_out <= clk;
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pc <= t_pc;
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end; --architecture logic
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end; --architecture logic
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