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[/] [mlite/] [trunk/] [vhdl/] [tbench.vhd] - Diff between revs 7 and 8
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Line 12... |
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mips_pack.all;
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use work.mips_pack.all;
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entity tbench is
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entity tbench is
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port(clk_out : out std_logic);
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end; --entity tbench
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end; --entity tbench
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architecture logic of tbench is
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architecture logic of tbench is
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component mips_cpu
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component mips_cpu
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mem_write => mem_write,
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mem_write => mem_write,
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mem_address => mem_address(15 downto 0),
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mem_address => mem_address(15 downto 0),
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mem_data_w => mem_data_w,
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mem_data_w => mem_data_w,
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mem_data_r => mem_data_r);
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mem_data_r => mem_data_r);
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clk_out <= clk;
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end; --architecture logic
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end; --architecture logic
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