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Line 39... |
signal delay_read_reg : std_logic_vector(9 downto 0);
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signal delay_read_reg : std_logic_vector(9 downto 0);
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signal bits_read_reg : std_logic_vector(3 downto 0);
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signal bits_read_reg : std_logic_vector(3 downto 0);
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signal data_read_reg : std_logic_vector(7 downto 0);
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signal data_read_reg : std_logic_vector(7 downto 0);
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signal data_save_reg : std_logic_vector(17 downto 0);
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signal data_save_reg : std_logic_vector(17 downto 0);
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signal busy_write_sig : std_logic;
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signal busy_write_sig : std_logic;
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signal read_value_reg : std_logic_vector(7 downto 0);
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signal read_value_reg : std_logic_vector(6 downto 0);
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signal uart_read2 : std_logic;
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signal uart_read2 : std_logic;
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begin
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begin
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uart_proc: process(clk, reset, enable_read, enable_write, data_in,
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uart_proc: process(clk, reset, enable_read, enable_write, data_in,
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| Line 53... |
Line 53... |
busy_write_sig, uart_read)
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busy_write_sig, uart_read)
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constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
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constant COUNT_VALUE : std_logic_vector(9 downto 0) :=
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-- "0100011110"; --33MHz/2/57600Hz = 0x11e
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-- "0100011110"; --33MHz/2/57600Hz = 0x11e
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-- "1101100100"; --50MHz/57600Hz = 0x364
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-- "1101100100"; --50MHz/57600Hz = 0x364
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"0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
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"0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2
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-- "0011011001"; --12.5MHz/57600Hz = 0xd9
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-- "0000000100"; --for debug (shorten read_value_reg)
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-- "0000000100"; --for debug (shorten read_value_reg)
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begin
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begin
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uart_read2 <= read_value_reg(read_value_reg'length - 1);
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uart_read2 <= read_value_reg(read_value_reg'length - 1);
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if reset = '1' then
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if reset = '1' then
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data_write_reg <= ZERO(8 downto 1) & '1';
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data_write_reg <= ZERO(8 downto 1) & '1';
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bits_write_reg <= "0000";
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bits_write_reg <= "0000";
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delay_write_reg <= ZERO(9 downto 0);
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delay_write_reg <= ZERO(9 downto 0);
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read_value_reg <= ONES(7 downto 0);
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read_value_reg <= ONES(read_value_reg'length-1 downto 0);
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data_read_reg <= ZERO(7 downto 0);
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data_read_reg <= ZERO(7 downto 0);
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bits_read_reg <= "0000";
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bits_read_reg <= "0000";
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delay_read_reg <= ZERO(9 downto 0);
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delay_read_reg <= ZERO(9 downto 0);
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data_save_reg <= ZERO(17 downto 0);
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data_save_reg <= ZERO(17 downto 0);
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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