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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Implements the UART.
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-- Implements the UART.
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-- Stalls the CPU until the charater has been transmitted.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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uart_write : out std_logic;
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uart_write : out std_logic;
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pause : out std_logic);
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pause : out std_logic);
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end; --entity ram
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end; --entity ram
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architecture logic of uart is
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architecture logic of uart is
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signal uart_data_reg : std_logic_vector(8 downto 0);
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signal data_reg : std_logic_vector(8 downto 0);
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signal uart_bits_reg : std_logic_vector(3 downto 0);
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signal bits_reg : std_logic_vector(3 downto 0);
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signal uart_div_reg : std_logic_vector(7 downto 0);
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signal div_reg : std_logic_vector(9 downto 0);
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begin
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begin
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uart_proc: process(clk, reset, uart_sel, data,
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uart_proc: process(clk, reset, data_reg, bits_reg, div_reg, uart_sel, data)
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uart_data_reg, uart_bits_reg, uart_div_reg)
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constant DIV_VALUE : std_logic_vector(9 downto 0) :=
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variable uart_data_next : std_logic_vector(8 downto 0);
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"0100011110"; --33MHz/2/57600Hz = 0x11e
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variable uart_bits_next : std_logic_vector(3 downto 0);
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-- "0000000010"; --for debug
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variable uart_div_next : std_logic_vector(7 downto 0);
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variable data_next : std_logic_vector(8 downto 0);
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variable bits_next : std_logic_vector(3 downto 0);
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variable div_next : std_logic_vector(9 downto 0);
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begin
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begin
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uart_data_next := uart_data_reg;
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data_next := data_reg;
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uart_bits_next := uart_bits_reg;
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bits_next := bits_reg;
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uart_div_next := uart_div_reg;
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div_next := div_reg;
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if uart_bits_reg = "0000" and uart_sel = '1' then
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if uart_sel = '1' then
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uart_data_next := data & '0';
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data_next := data & '0';
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uart_bits_next := "1010";
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bits_next := "1010";
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uart_div_next := ZERO(7 downto 0);
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div_next := ZERO(9 downto 0);
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elsif uart_bits_reg /= "0000" and
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elsif div_reg = DIV_VALUE then
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((log_file /= "UNUSED" and uart_div_reg = "00000010") or
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data_next := '1' & data_reg(8 downto 1);
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(log_file = "UNUSED" and uart_div_reg = "10001100")) then
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if bits_reg /= "0000" then
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uart_data_next := '1' & uart_data_reg(8 downto 1);
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bits_next := bits_reg - 1;
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uart_bits_next := uart_bits_reg - 1;
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end if;
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uart_div_next := ZERO(7 downto 0);
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div_next := ZERO(9 downto 0);
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else
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else
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uart_div_next := uart_div_reg + 1;
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div_next := div_reg + 1;
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end if;
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end if;
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if reset = '1' then
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if reset = '1' then
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uart_data_next := ONES(8 downto 0);
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data_reg <= ZERO(8 downto 0);
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uart_bits_next := "0000";
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bits_reg <= "0000";
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uart_div_next := ZERO(7 downto 0);
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div_reg <= ZERO(9 downto 0);
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elsif rising_edge(clk) then
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data_reg <= data_next;
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bits_reg <= bits_next;
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div_reg <= div_next;
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end if;
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end if;
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if rising_edge(clk) then
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uart_write <= data_reg(0);
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uart_data_reg <= uart_data_next;
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if uart_sel = '0' and bits_reg /= "0000"
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uart_bits_reg <= uart_bits_next;
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and log_file = "UNUSED"
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uart_div_reg <= uart_div_next;
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then
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end if;
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uart_write <= uart_data_reg(0);
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if uart_bits_reg = ZERO(7 downto 0) or uart_sel = '1' then
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pause <= '0';
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elsif log_file = "UNUSED" then
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pause <= '1';
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pause <= '1';
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else
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else
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-- pause <= '1';
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pause <= '0';
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pause <= '0';
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end if;
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end if;
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end process;
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end process;
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uart_logger:
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uart_logger:
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c := character'val(index);
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c := character'val(index);
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write(hex_file_line, c);
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write(hex_file_line, c);
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line_length := line_length + 1;
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line_length := line_length + 1;
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end if;
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end if;
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if index = 10 or line_length >= 72 then
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if index = 10 or line_length >= 72 then
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--The following line had to be commented out for synthesis
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writeline(store_file, hex_file_line);
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writeline(store_file, hex_file_line);
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line_length := 0;
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line_length := 0;
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end if;
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end if;
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end if; --uart_sel
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end if; --uart_sel
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end if; --rising_edge(clk)
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end if; --rising_edge(clk)
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