| Line 1... |
Line 1... |
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
---- multiplier_core ----
|
---- mod_sim_exp_core ----
|
---- ----
|
---- ----
|
---- This file is part of the ----
|
---- This file is part of the ----
|
---- Modular Simultaneous Exponentiation Core project ----
|
---- Modular Simultaneous Exponentiation Core project ----
|
---- http://www.opencores.org/cores/mod_sim_exp/ ----
|
---- http://www.opencores.org/cores/mod_sim_exp/ ----
|
---- ----
|
---- ----
|
---- Description ----
|
---- Description ----
|
---- toplevel of a modular simultaneous exponentiation core ----
|
---- toplevel of a modular simultaneous exponentiation core ----
|
---- using a pipelined montgommery multiplier with split ----
|
---- using a pipelined montgommery multiplier with split ----
|
---- pipeline support and auto-run support ----
|
---- pipeline and auto-run support ----
|
---- ----
|
---- ----
|
---- Dependencies: ----
|
---- Dependencies: ----
|
---- - mont_mult_sys_pipeline ----
|
---- - mont_mult_sys_pipeline ----
|
---- - operand_mem ----
|
---- - operand_mem ----
|
---- - fifo_primitive ----
|
---- - fifo_primitive ----
|
| Line 53... |
Line 53... |
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
|
|
library mod_sim_exp;
|
library mod_sim_exp;
|
use mod_sim_exp.mod_sim_exp_pkg.all;
|
use mod_sim_exp.mod_sim_exp_pkg.all;
|
|
|
|
-- toplevel of the modular simultaneous exponentiation core
|
entity multiplier_core is
|
-- contains an operand and modulus ram, multiplier, an exponent fifo
|
|
-- and control logic
|
|
entity mod_sim_exp_core is
|
port(
|
port(
|
clk : in std_logic;
|
clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
-- operand memory interface (plb shared memory)
|
-- operand memory interface (plb shared memory)
|
write_enable : in std_logic;
|
write_enable : in std_logic; -- write data to operand ram
|
data_in : in std_logic_vector (31 downto 0);
|
data_in : in std_logic_vector (31 downto 0); -- operand ram data in
|
rw_address : in std_logic_vector (8 downto 0);
|
rw_address : in std_logic_vector (8 downto 0); -- operand ram address bus
|
data_out : out std_logic_vector (31 downto 0);
|
data_out : out std_logic_vector (31 downto 0); -- operand ram data out
|
collision : out std_logic;
|
collision : out std_logic; -- write collision
|
-- op_sel fifo interface
|
-- op_sel fifo interface
|
fifo_din : in std_logic_vector (31 downto 0);
|
fifo_din : in std_logic_vector (31 downto 0); -- exponent fifo data in
|
fifo_push : in std_logic;
|
fifo_push : in std_logic; -- push data in exponent fifo
|
fifo_full : out std_logic;
|
fifo_full : out std_logic; -- high if fifo is full
|
fifo_nopush : out std_logic;
|
fifo_nopush : out std_logic; -- high if error during push
|
-- ctrl signals
|
-- control signals
|
start : in std_logic;
|
start : in std_logic; -- start multiplication/exponentiation
|
run_auto : in std_logic;
|
run_auto : in std_logic; -- single multiplication if low, exponentiation if high
|
ready : out std_logic;
|
ready : out std_logic; -- calculations done
|
x_sel_single : in std_logic_vector (1 downto 0);
|
x_sel_single : in std_logic_vector (1 downto 0); -- single multiplication x operand selection
|
y_sel_single : in std_logic_vector (1 downto 0);
|
y_sel_single : in std_logic_vector (1 downto 0); -- single multiplication y operand selection
|
dest_op_single : in std_logic_vector (1 downto 0);
|
dest_op_single : in std_logic_vector (1 downto 0); -- result destination operand selection
|
p_sel : in std_logic_vector (1 downto 0);
|
p_sel : in std_logic_vector (1 downto 0); -- pipeline part selection
|
calc_time : out std_logic
|
calc_time : out std_logic
|
);
|
);
|
end multiplier_core;
|
end mod_sim_exp_core;
|
|
|
|
|
architecture Behavioral of multiplier_core is
|
architecture Structural of mod_sim_exp_core is
|
signal xy_i : std_logic_vector(1535 downto 0);
|
constant n : integer := 1536;
|
signal x_i : std_logic;
|
constant t : integer := 96;
|
signal m : std_logic_vector(1535 downto 0);
|
constant tl : integer := 32;
|
signal r : std_logic_vector(1535 downto 0);
|
|
|
|
signal op_sel : std_logic_vector(1 downto 0);
|
-- data busses
|
signal result_dest_op_i : std_logic_vector(1 downto 0);
|
signal xy : std_logic_vector(n-1 downto 0); -- x and y operand data bus RAM -> multiplier
|
|
signal m : std_logic_vector(n-1 downto 0); -- modulus data bus RAM -> multiplier
|
|
signal r : std_logic_vector(n-1 downto 0); -- result data bus RAM <- multiplier
|
|
|
|
-- control signals
|
|
signal op_sel : std_logic_vector(1 downto 0); -- operand selection
|
|
signal result_dest_op : std_logic_vector(1 downto 0); -- result destination operand
|
signal mult_ready : std_logic;
|
signal mult_ready : std_logic;
|
signal start_mult : std_logic;
|
signal start_mult : std_logic;
|
signal load_op : std_logic;
|
signal load_op : std_logic;
|
signal load_x_i : std_logic;
|
signal load_x : std_logic;
|
signal load_m : std_logic;
|
signal load_m : std_logic;
|
signal load_result : std_logic;
|
signal load_result : std_logic;
|
|
|
|
-- fifo signals
|
signal fifo_empty : std_logic;
|
signal fifo_empty : std_logic;
|
signal fifo_pop : std_logic;
|
signal fifo_pop : std_logic;
|
signal fifo_nopop : std_logic;
|
signal fifo_nopop : std_logic;
|
signal fifo_dout : std_logic_vector(31 downto 0);
|
signal fifo_dout : std_logic_vector(31 downto 0);
|
--signal fifo_push : std_logic;
|
|
|
|
constant n : integer := 1536;
|
|
constant t : integer := 96;
|
|
constant tl : integer := 32;
|
|
|
|
begin
|
begin
|
|
|
-- The actual multiplier
|
-- The actual multiplier
|
the_multiplier : mont_mult_sys_pipeline generic map(
|
the_multiplier : mont_mult_sys_pipeline
|
|
generic map(
|
n => n,
|
n => n,
|
nr_stages => t, --(divides n, bits_low & (n-bits_low))
|
nr_stages => t, --(divides n, bits_low & (n-bits_low))
|
stages_low => tl
|
stages_low => tl
|
)
|
)
|
port map(
|
port map(
|
core_clk => clk,
|
core_clk => clk,
|
xy => xy_i,
|
xy => xy,
|
m => m,
|
m => m,
|
r => r,
|
r => r,
|
start => start_mult,
|
start => start_mult,
|
reset => reset,
|
reset => reset,
|
p_sel => p_sel,
|
p_sel => p_sel,
|
load_x => load_x_i,
|
load_x => load_x,
|
ready => mult_ready
|
ready => mult_ready
|
);
|
);
|
|
|
-- Block ram memory for storing the operands and the modulus
|
-- Block ram memory for storing the operands and the modulus
|
the_memory : operand_mem port map(
|
the_memory : operand_mem
|
|
port map(
|
data_in => data_in,
|
data_in => data_in,
|
data_out => data_out,
|
data_out => data_out,
|
rw_address => rw_address,
|
rw_address => rw_address,
|
op_sel => op_sel,
|
op_sel => op_sel,
|
xy_out => xy_i,
|
xy_out => xy,
|
m => m,
|
m => m,
|
result_in => r,
|
result_in => r,
|
load_op => load_op,
|
load_op => load_op,
|
load_m => load_m,
|
load_m => load_m,
|
load_result => load_result,
|
load_result => load_result,
|
result_dest_op => result_dest_op_i,
|
result_dest_op => result_dest_op,
|
collision => collision,
|
collision => collision,
|
clk => clk
|
clk => clk
|
);
|
);
|
|
|
load_op <= write_enable when (rw_address(8) = '0') else '0';
|
load_op <= write_enable when (rw_address(8) = '0') else '0';
|
load_m <= write_enable when (rw_address(8) = '1') else '0';
|
load_m <= write_enable when (rw_address(8) = '1') else '0';
|
result_dest_op_i <= dest_op_single when run_auto = '0' else "11"; -- in autorun mode we always store the result in operand3
|
result_dest_op <= dest_op_single when run_auto = '0' else "11"; -- in autorun mode we always store the result in operand3
|
|
|
-- A fifo for auto-run operand selection
|
-- A fifo for auto-run operand selection
|
the_exponent_fifo : fifo_primitive port map(
|
the_exponent_fifo : fifo_primitive
|
|
port map(
|
clk => clk,
|
clk => clk,
|
din => fifo_din,
|
din => fifo_din,
|
dout => fifo_dout,
|
dout => fifo_dout,
|
empty => fifo_empty,
|
empty => fifo_empty,
|
full => fifo_full,
|
full => fifo_full,
|
| Line 163... |
Line 168... |
nopop => fifo_nopop,
|
nopop => fifo_nopop,
|
nopush => fifo_nopush
|
nopush => fifo_nopush
|
);
|
);
|
|
|
-- The control logic for the core
|
-- The control logic for the core
|
the_control_unit : mont_ctrl port map(
|
the_control_unit : mont_ctrl
|
|
port map(
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
start => start,
|
start => start,
|
x_sel_single => x_sel_single,
|
x_sel_single => x_sel_single,
|
y_sel_single => y_sel_single,
|
y_sel_single => y_sel_single,
|
| Line 177... |
Line 183... |
read_buffer => fifo_pop,
|
read_buffer => fifo_pop,
|
buffer_noread => fifo_nopop,
|
buffer_noread => fifo_nopop,
|
done => ready,
|
done => ready,
|
calc_time => calc_time,
|
calc_time => calc_time,
|
op_sel => op_sel,
|
op_sel => op_sel,
|
load_x => load_x_i,
|
load_x => load_x,
|
load_result => load_result,
|
load_result => load_result,
|
start_multiplier => start_mult,
|
start_multiplier => start_mult,
|
multiplier_ready => mult_ready
|
multiplier_ready => mult_ready
|
);
|
);
|
|
|
end Behavioral;
|
end Structural;
|
|
|
No newline at end of file
|
No newline at end of file
|
