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& \verb|"xil_prim"| : use xilinx primitives & & \\
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& \verb|"xil_prim"| : use xilinx primitives & & \\
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& \verb|"generic"| : use general 32-bit RAMs & & \\
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& \verb|"generic"| : use general 32-bit RAMs & & \\
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& \verb|"asym"| : use asymmetric RAMs & & \\
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& \verb|"asym"| : use asymmetric RAMs & & \\
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& (For more information see \ref{subsec:RAM_and_FIFO}) & & \bigstrut[b] \\
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& (For more information see \ref{subsec:RAM_and_FIFO}) & & \bigstrut[b] \\
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\hline
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\hline
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\verb|C_DEVICE| & device manufacturer: & string & \verb|"xilinx"| \\
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\verb|C_FPGA_MAN| & device manufacturer: & string & \verb|"xilinx"| \\
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& \verb|"xilinx"| or \verb|"altera"| & & \bigstrut\\
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& \verb|"xilinx"| or \verb|"altera"| & & \bigstrut\\
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\hline
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\verb|C_BASEADDR| & base address for the IP core's memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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\verb|C_BASEADDR| & base address for the IP core's memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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\hline
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\hline
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\verb|C_HIGHADDR| & high address for the IP core's memory space & std\_logic\_vector & X"00000000" \bigstrut\\
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\verb|C_HIGHADDR| & high address for the IP core's memory space & std\_logic\_vector & X"00000000" \bigstrut\\
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