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[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] [vhdl/] [core/] [fifo_generic.vhd] - Diff between revs 54 and 55

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----  This file is part of the                                    ----
----  This file is part of the                                    ----
----    Modular Simultaneous Exponentiation Core project          ---- 
----    Modular Simultaneous Exponentiation Core project          ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----    http://www.opencores.org/cores/mod_sim_exp/               ---- 
----                                                              ---- 
----                                                              ---- 
----  Description                                                 ---- 
----  Description                                                 ---- 
----    behavorial description of a FIFO,                  ----
----    behavorial description of a FIFO, correctly inferred by   ----
-- Synthesizing Unit <fifo_generic>.
----    altera and xilinx.                                        ----
--    Related source file is "/dropbox/svn/mod_sim_exp/rtl/vhdl/core/fifo_generic.vhd".
----                                                              ----
--        aw = 8
----  Resources needed (xilinx):                                  ----
--        depth = 128
----    - RAM: (depth+1 * 32) bits                                ----
--WARNING:Xst:3035 - Index value(s) does not match array range for signal <RAM>, simulation mismatch.
----    - 2 adders/substractors                                   ----
--    Found 129x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.
----    - 2 comparators                                           ----
--    Found 8-bit register for signal <rd_addr>.
----    - 2 registers: aw bits  (for the address pointers)        ----
--    Found 1-bit register for signal <push_i_d>.
----    - 3 registers:  1 bit (for the flags)                     ----
--    Found 1-bit register for signal <nopop>.
 
--    Found 1-bit register for signal <nopush>.
 
--    Found 8-bit register for signal <wr_addr>.
 
--    Found 8-bit adder for signal <wr_addr[7]_GND_107_o_add_0_OUT> created at line 89.
 
--    Found 8-bit adder for signal <rd_addr[7]_GND_107_o_add_10_OUT> created at line 114.
 
--    Found 8-bit comparator equal for signal <wr_addr[7]_rd_addr[7]_equal_2_o> created at line 89
 
--    Found 8-bit comparator equal for signal <empty_i> created at line 93
 
--    Summary:
 
--  inferred   1 RAM(s).
 
--  inferred   2 Adder/Subtractor(s).
 
--  inferred  19 D-type flip-flop(s).
 
--  inferred   2 Comparator(s).
 
--Unit <fifo_generic> synthesized.
 
----                                                              ---- 
----                                                              ---- 
----  Authors:                                                    ----
----  Authors:                                                    ----
----      - Geoffrey Ottoy, DraMCo research group                 ----
----      - Geoffrey Ottoy, DraMCo research group                 ----
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
----      - Jonas De Craene, JonasDC@opencores.org                ---- 
----                                                              ---- 
----                                                              ---- 

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