URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 89 |
Rev 90 |
Line 136... |
Line 136... |
ramblock: dpram_generic
|
ramblock: dpram_generic
|
generic map(
|
generic map(
|
depth => depth+1
|
depth => depth+1
|
)
|
)
|
port map(
|
port map(
|
|
clk => clk,
|
-- write port
|
-- write port
|
clkA => clk,
|
waddr => wr_addr,
|
waddrA => wr_addr,
|
we => push_i_d,
|
weA => push_i_d,
|
din => din,
|
dinA => din,
|
|
-- read port
|
-- read port
|
clkB => clk,
|
raddr => rd_addr,
|
raddrB => rd_addr,
|
dout => dout
|
doutB => dout
|
|
);
|
);
|
|
|
end arch;
|
end arch;
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.