| Line 61... |
Line 61... |
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entity mod_sim_exp_core_tb is
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entity mod_sim_exp_core_tb is
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end mod_sim_exp_core_tb;
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end mod_sim_exp_core_tb;
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architecture test of mod_sim_exp_core_tb is
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architecture test of mod_sim_exp_core_tb is
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constant nr_stages : integer := 96;
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal reset : std_logic := '1';
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signal reset : std_logic := '1';
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file input : text open read_mode is "src/sim_input.txt";
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file input : text open read_mode is "src/sim_input.txt";
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file output : text open write_mode is "out/sim_output.txt";
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file output : text open write_mode is "out/sim_output.txt";
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| Line 253... |
Line 252... |
writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'("base width: "));
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write(Lw, string'("base width: "));
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write(Lw, base_width);
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write(Lw, base_width);
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writeline(output, Lw);
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writeline(output, Lw);
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case (base_width) is
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case (base_width) is
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when 1536 => when 1024 => when 512 =>
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when nr_bits_total => when nr_bits_high => when nr_bits_low =>
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when others =>
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when others =>
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write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
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write(Lw, string'("=> incompatible base width!!!")); writeline(output, Lw);
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assert false report "incompatible base width!!!" severity failure;
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assert false report "incompatible base width!!!" severity failure;
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end case;
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end case;
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| Line 330... |
Line 329... |
----------------------------------------
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----------------------------------------
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'("----- Selecting pipeline: "));
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write(Lw, string'("----- Selecting pipeline: "));
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writeline(output, Lw);
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writeline(output, Lw);
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case (base_width) is
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case (base_width) is
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when 1536 => core_p_sel <= "11"; write(Lw, string'(" Full pipeline selected"));
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when nr_bits_total => core_p_sel <= "11"; write(Lw, string'(" Full pipeline selected"));
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when 1024 => core_p_sel <= "10"; write(Lw, string'(" Upper pipeline selected"));
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when nr_bits_high => core_p_sel <= "10"; write(Lw, string'(" Upper pipeline selected"));
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when 512 => core_p_sel <= "01"; write(Lw, string'(" Lower pipeline selected"));
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when nr_bits_low => core_p_sel <= "01"; write(Lw, string'(" Lower pipeline selected"));
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when others =>
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when others =>
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write(Lw, string'(" Invallid bitwidth for design"));
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write(Lw, string'(" Invallid bitwidth for design"));
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assert false report "impossible basewidth!" severity failure;
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assert false report "impossible basewidth!" severity failure;
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end case;
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end case;
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writeline(output, Lw);
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writeline(output, Lw);
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| Line 425... |
Line 424... |
writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(ToString(timer)));
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write(Lw, string'(ToString(timer)));
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => expected time is "));
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write(Lw, string'(" => expected time is "));
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write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
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write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
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writeline(output, Lw);
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writeline(output, Lw);
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if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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if (gt0(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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write(Lw, string'(" => gt0 is correct!")); writeline(output, Lw);
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write(Lw, string'(" => gt0 is correct!")); writeline(output, Lw);
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else
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else
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write(Lw, string'(" => Error: gt0 is incorrect!!!")); writeline(output, Lw);
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write(Lw, string'(" => Error: gt0 is incorrect!!!")); writeline(output, Lw);
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| Line 458... |
Line 457... |
writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(ToString(timer)));
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write(Lw, string'(ToString(timer)));
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => expected time is "));
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write(Lw, string'(" => expected time is "));
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write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
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write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
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writeline(output, Lw);
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writeline(output, Lw);
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if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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if (gt1(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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write(Lw, string'(" => gt1 is correct!")); writeline(output, Lw);
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write(Lw, string'(" => gt1 is correct!")); writeline(output, Lw);
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else
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else
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write(Lw, string'(" => Error: gt1 is incorrect!!!")); writeline(output, Lw);
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write(Lw, string'(" => Error: gt1 is incorrect!!!")); writeline(output, Lw);
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| Line 491... |
Line 490... |
writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(ToString(timer)));
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write(Lw, string'(ToString(timer)));
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => expected time is "));
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write(Lw, string'(" => expected time is "));
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write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
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write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
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writeline(output, Lw);
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writeline(output, Lw);
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if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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if (R(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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write(Lw, string'(" => (R)mod m is correct!")); writeline(output, Lw);
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write(Lw, string'(" => (R)mod m is correct!")); writeline(output, Lw);
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else
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else
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write(Lw, string'(" => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
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write(Lw, string'(" => Error: (R)mod m is incorrect!!!")); writeline(output, Lw);
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| Line 524... |
Line 523... |
writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(ToString(timer)));
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write(Lw, string'(ToString(timer)));
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => expected time is "));
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write(Lw, string'(" => expected time is "));
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write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
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write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
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writeline(output, Lw);
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writeline(output, Lw);
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if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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if (gt01(base_width-1 downto 0) = data_read(base_width-1 downto 0)) then
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write(Lw, string'(" => gt01 is correct!")); writeline(output, Lw);
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write(Lw, string'(" => gt01 is correct!")); writeline(output, Lw);
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else
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else
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write(Lw, string'(" => Error: gt01 is incorrect!!!")); writeline(output, Lw);
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write(Lw, string'(" => Error: gt01 is incorrect!!!")); writeline(output, Lw);
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| Line 570... |
Line 569... |
waitclk(10);
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waitclk(10);
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(ToString(timer)));
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write(Lw, string'(ToString(timer)));
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => expected time is "));
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write(Lw, string'(" => expected time is "));
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write(Lw, ((nr_stages+(2*(base_width-1)))*clk_period*7*exponent_width)/4);
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write(Lw, ((nr_stages_total+(2*(base_width-1)))*clk_period*7*exponent_width)/4);
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => Done"));
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write(Lw, string'(" => Done"));
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core_run_auto <= '0';
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core_run_auto <= '0';
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writeline(output, Lw);
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writeline(output, Lw);
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| Line 611... |
Line 610... |
writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(" => calc time is "));
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write(Lw, string'(ToString(timer)));
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write(Lw, string'(ToString(timer)));
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => expected time is "));
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write(Lw, string'(" => expected time is "));
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write(Lw, (nr_stages+(2*(base_width-1)))*clk_period);
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write(Lw, (nr_stages_total+(2*(base_width-1)))*clk_period);
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writeline(output, Lw);
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writeline(output, Lw);
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when 12 => -- check with result
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when 12 => -- check with result
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hread(L, result(base_width-1 downto 0), good_value);
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hread(L, result(base_width-1 downto 0), good_value);
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assert good_value report "Can not read result! (wrong lenght?)" severity failure;
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assert good_value report "Can not read result! (wrong lenght?)" severity failure;
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