Line 92... |
Line 92... |
signal core_fifo_push : std_logic;
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signal core_fifo_push : std_logic;
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------------------------------------------------------------------
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------------------------------------------------------------------
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-- Signals for multiplier core control
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-- Signals for multiplier core control
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------------------------------------------------------------------
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------------------------------------------------------------------
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signal core_start : std_logic;
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signal core_start : std_logic;
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signal core_run_auto : std_logic;
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signal core_exp_m : std_logic;
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signal core_p_sel : std_logic_vector(1 downto 0);
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signal core_p_sel : std_logic_vector(1 downto 0);
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signal core_dest_op_single : std_logic_vector(1 downto 0);
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signal core_dest_op_single : std_logic_vector(1 downto 0);
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signal core_x_sel_single : std_logic_vector(1 downto 0);
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signal core_x_sel_single : std_logic_vector(1 downto 0);
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signal core_y_sel_single : std_logic_vector(1 downto 0);
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signal core_y_sel_single : std_logic_vector(1 downto 0);
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signal calc_time : std_logic;
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signal calc_time : std_logic;
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Line 231... |
Line 231... |
-- fifo
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-- fifo
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core_fifo_din <= x"00000000";
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core_fifo_din <= x"00000000";
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core_fifo_push <= '0';
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core_fifo_push <= '0';
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-- control
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-- control
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core_start <= '0';
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core_start <= '0';
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core_run_auto <= '0';
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core_exp_m <= '0';
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core_x_sel_single <= "00";
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core_x_sel_single <= "00";
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core_y_sel_single <= "01";
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core_y_sel_single <= "01";
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core_dest_op_single <= "01";
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core_dest_op_single <= "01";
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core_p_sel <= "11";
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core_p_sel <= "11";
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Line 568... |
Line 568... |
-- start exponentiation
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-- start exponentiation
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------------------------
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------------------------
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'("----- Starting exponentiation: "));
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write(Lw, string'("----- Starting exponentiation: "));
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writeline(output, Lw);
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writeline(output, Lw);
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core_run_auto <= '1';
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core_exp_m <= '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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timer := NOW;
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timer := NOW;
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core_start <= '1';
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core_start <= '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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core_start <= '0';
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core_start <= '0';
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Line 584... |
Line 584... |
writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => expected time is "));
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write(Lw, string'(" => expected time is "));
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write(Lw, ((C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD*7*exponent_width)/4);
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write(Lw, ((C_NR_STAGES_TOTAL+(2*(base_width-1)))*CLK_PERIOD*7*exponent_width)/4);
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writeline(output, Lw);
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writeline(output, Lw);
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write(Lw, string'(" => Done"));
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write(Lw, string'(" => Done"));
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core_run_auto <= '0';
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core_exp_m <= '0';
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writeline(output, Lw);
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writeline(output, Lw);
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-- post-computations
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-- post-computations
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---------------------
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---------------------
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writeline(output, Lw);
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writeline(output, Lw);
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Line 687... |
Line 687... |
fifo_push => core_fifo_push,
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fifo_push => core_fifo_push,
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fifo_full => core_fifo_full,
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fifo_full => core_fifo_full,
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fifo_nopush => core_fifo_nopush,
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fifo_nopush => core_fifo_nopush,
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-- ctrl signals
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-- ctrl signals
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start => core_start,
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start => core_start,
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run_auto => core_run_auto,
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exp_m => core_exp_m,
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ready => core_ready,
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ready => core_ready,
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x_sel_single => core_x_sel_single,
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x_sel_single => core_x_sel_single,
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y_sel_single => core_y_sel_single,
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y_sel_single => core_y_sel_single,
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dest_op_single => core_dest_op_single,
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dest_op_single => core_dest_op_single,
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p_sel => core_p_sel,
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p_sel => core_p_sel,
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