Line 75... |
Line 75... |
constant C_NR_BITS_TOTAL : integer := 1536;
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constant C_NR_BITS_TOTAL : integer := 1536;
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constant C_NR_STAGES_TOTAL : integer := 96;
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constant C_NR_STAGES_TOTAL : integer := 96;
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constant C_NR_STAGES_LOW : integer := 32;
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constant C_NR_STAGES_LOW : integer := 32;
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constant C_SPLIT_PIPELINE : boolean := true;
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constant C_SPLIT_PIPELINE : boolean := true;
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constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16
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constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16
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constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options
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constant C_MEM_STYLE : string := "asym"; -- xil_prim, generic, asym are valid options
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constant C_DEVICE : string := "xilinx"; -- xilinx, altera are valid options
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constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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-- extra calculated constants
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-- extra calculated constants
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constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
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constant NR_BITS_LOW : integer := (C_NR_BITS_TOTAL/C_NR_STAGES_TOTAL)*C_NR_STAGES_LOW;
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constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
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constant NR_BITS_HIGH : integer := C_NR_BITS_TOTAL-NR_BITS_LOW;
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Line 677... |
Line 677... |
C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_FIFO_DEPTH => C_FIFO_DEPTH,
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C_FIFO_DEPTH => C_FIFO_DEPTH,
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C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
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C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
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C_DEVICE => C_DEVICE -- xilinx, altera are valid options
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C_FPGA_MAN => C_FPGA_MAN -- xilinx, altera are valid options
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)
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)
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port map(
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port map(
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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-- operand memory interface (plb shared memory)
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-- operand memory interface (plb shared memory)
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Line 702... |
Line 702... |
x_sel_single => core_x_sel_single,
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x_sel_single => core_x_sel_single,
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y_sel_single => core_y_sel_single,
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y_sel_single => core_y_sel_single,
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dest_op_single => core_dest_op_single,
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dest_op_single => core_dest_op_single,
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p_sel => core_p_sel,
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p_sel => core_p_sel,
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calc_time => calc_time,
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calc_time => calc_time,
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modulus_sel => "0"
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modulus_sel => '0'
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);
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);
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end test;
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end test;
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No newline at end of file
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No newline at end of file
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