| Line 77... |
Line 77... |
------------------------------------------------------------------
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------------------------------------------------------------------
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constant C_NR_BITS_TOTAL : integer := 1536;
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constant C_NR_BITS_TOTAL : integer := 1536;
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constant C_NR_STAGES_TOTAL : integer := 96;
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constant C_NR_STAGES_TOTAL : integer := 96;
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constant C_NR_STAGES_LOW : integer := 32;
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constant C_NR_STAGES_LOW : integer := 32;
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constant C_SPLIT_PIPELINE : boolean := true;
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constant C_SPLIT_PIPELINE : boolean := true;
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constant C_FIFO_DEPTH : integer := 32; -- set to (maximum exponent width)/16
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constant C_FIFO_AW : integer := 7; -- set to log2( (maximum exponent width)/16 )
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constant C_MEM_STYLE : string := "generic"; -- xil_prim, generic, asym are valid options
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constant C_MEM_STYLE : string := "xil_prim"; -- xil_prim, generic, asym are valid options
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constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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constant C_FPGA_MAN : string := "xilinx"; -- xilinx, altera are valid options
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constant C_BASEADDR : std_logic_vector(0 to 31) := x"A0000000";
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constant C_BASEADDR : std_logic_vector(0 to 31) := x"A0000000";
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constant C_HIGHADDR : std_logic_vector(0 to 31) := x"A0007FFF";
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constant C_HIGHADDR : std_logic_vector(0 to 31) := x"A0007FFF";
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-- extra calculated constants
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-- extra calculated constants
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| Line 819... |
Line 819... |
generic map(
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generic map(
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C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_BITS_TOTAL => C_NR_BITS_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_TOTAL => C_NR_STAGES_TOTAL,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_NR_STAGES_LOW => C_NR_STAGES_LOW,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_SPLIT_PIPELINE => C_SPLIT_PIPELINE,
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C_FIFO_DEPTH => C_FIFO_DEPTH,
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C_FIFO_AW => C_FIFO_AW,
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C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
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C_MEM_STYLE => C_MEM_STYLE, -- xil_prim, generic, asym are valid options
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C_FPGA_MAN => C_FPGA_MAN, -- xilinx, altera are valid options
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C_FPGA_MAN => C_FPGA_MAN, -- xilinx, altera are valid options
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C_BASEADDR => C_BASEADDR,
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C_BASEADDR => C_BASEADDR,
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C_HIGHADDR => C_HIGHADDR
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C_HIGHADDR => C_HIGHADDR
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)
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)
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port map(
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port map(
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--USER ports
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--USER ports
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calc_time => calc_time,
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calc_time => calc_time,
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IntrEvent => IntrEvent,
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IntrEvent => IntrEvent,
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core_clk => core_clk,
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-------------------------
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-------------------------
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-- AXI4lite interface
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-- AXI4lite interface
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-------------------------
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-------------------------
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--- Global signals
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--- Global signals
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S_AXI_ACLK => S_AXI_ACLK,
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S_AXI_ACLK => S_AXI_ACLK,
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